New process technology for a 4 Mbit SRAM with polysilicon load resistor cell

K. Yuzuriha, K. Ichinose, T. Mukai, Y. Kohno, M. Shimizu, M. Inuishi, T. Matsukawa

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

A 4-Mb SRAM memory cell has been successfully developed by using four-level polysilicon and two-level aluminum process technologies. Self-aligned contact with the pad polysilicon, silicide formation, thin polysilicon layer for high resistance, and implanted buried barrier technology were used to realize a small memory cell area (3.5 μm × 5.3 μm), low standby current (<1 μA), high stability, and high soft-error immunity.

Original languageEnglish
Pages (from-to)61-62
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 1989 Dec 1
Externally publishedYes
EventNinth Symposium on VLSI Technology 1989 - Digest of Technical Papers - Kyoto, Jpn
Duration: 1989 May 221989 May 25

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Yuzuriha, K., Ichinose, K., Mukai, T., Kohno, Y., Shimizu, M., Inuishi, M., & Matsukawa, T. (1989). New process technology for a 4 Mbit SRAM with polysilicon load resistor cell. Digest of Technical Papers - Symposium on VLSI Technology, 61-62.