A 4-Mb SRAM memory cell has been successfully developed by using four-level polysilicon and two-level aluminum process technologies. Self-aligned contact with the pad polysilicon, silicide formation, thin polysilicon layer for high resistance, and implanted buried barrier technology were used to realize a small memory cell area (3.5 μm × 5.3 μm), low standby current (<1 μA), high stability, and high soft-error immunity.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 1989 Dec 1|
|Event||Ninth Symposium on VLSI Technology 1989 - Digest of Technical Papers - Kyoto, Jpn|
Duration: 1989 May 22 → 1989 May 25
ASJC Scopus subject areas
- Electrical and Electronic Engineering