New process technology for a 4 Mbit SRAM with polysilicon load resistor cell

K. Yuzuriha; K. Ichinose; T. Mukai; Y. Kohno; M. Shimizu; M. Inuishi; T. Matsukawa

New process technology for a 4 Mbit SRAM with polysilicon load resistor cell

K. Yuzuriha, K. Ichinose, T. Mukai, Y. Kohno, M. Shimizu, M. Inuishi, T. Matsukawa

Research output: Contribution to journal › Conference article › peer-review

Abstract

A 4-Mb SRAM memory cell has been successfully developed by using four-level polysilicon and two-level aluminum process technologies. Self-aligned contact with the pad polysilicon, silicide formation, thin polysilicon layer for high resistance, and implanted buried barrier technology were used to realize a small memory cell area (3.5 μm × 5.3 μm), low standby current (<1 μA), high stability, and high soft-error immunity.

Original language	English
Pages (from-to)	61-62
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
Publication status	Published - 1989 Dec 1
Externally published	Yes
Event	Ninth Symposium on VLSI Technology 1989 - Digest of Technical Papers - Kyoto, Jpn Duration: 1989 May 22 → 1989 May 25

ASJC Scopus subject areas

Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'New process technology for a 4 Mbit SRAM with polysilicon load resistor cell'. Together they form a unique fingerprint.

Cite this

@article{ff2bd1b97cef47c087b32597a9747fa7,

title = "New process technology for a 4 Mbit SRAM with polysilicon load resistor cell",

abstract = "A 4-Mb SRAM memory cell has been successfully developed by using four-level polysilicon and two-level aluminum process technologies. Self-aligned contact with the pad polysilicon, silicide formation, thin polysilicon layer for high resistance, and implanted buried barrier technology were used to realize a small memory cell area (3.5 μm × 5.3 μm), low standby current (<1 μA), high stability, and high soft-error immunity.",

author = "K. Yuzuriha and K. Ichinose and T. Mukai and Y. Kohno and M. Shimizu and M. Inuishi and T. Matsukawa",

year = "1989",

month = dec,

day = "1",

language = "English",

pages = "61--62",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Ninth Symposium on VLSI Technology 1989 - Digest of Technical Papers ; Conference date: 22-05-1989 Through 25-05-1989",

}

TY - JOUR

T1 - New process technology for a 4 Mbit SRAM with polysilicon load resistor cell

AU - Yuzuriha, K.

AU - Ichinose, K.

AU - Mukai, T.

AU - Kohno, Y.

AU - Shimizu, M.

AU - Inuishi, M.

AU - Matsukawa, T.

PY - 1989/12/1

Y1 - 1989/12/1

N2 - A 4-Mb SRAM memory cell has been successfully developed by using four-level polysilicon and two-level aluminum process technologies. Self-aligned contact with the pad polysilicon, silicide formation, thin polysilicon layer for high resistance, and implanted buried barrier technology were used to realize a small memory cell area (3.5 μm × 5.3 μm), low standby current (<1 μA), high stability, and high soft-error immunity.

AB - A 4-Mb SRAM memory cell has been successfully developed by using four-level polysilicon and two-level aluminum process technologies. Self-aligned contact with the pad polysilicon, silicide formation, thin polysilicon layer for high resistance, and implanted buried barrier technology were used to realize a small memory cell area (3.5 μm × 5.3 μm), low standby current (<1 μA), high stability, and high soft-error immunity.

UR - http://www.scopus.com/inward/record.url?scp=0024906248&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024906248&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0024906248

SP - 61

EP - 62

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

SN - 0743-1562

T2 - Ninth Symposium on VLSI Technology 1989 - Digest of Technical Papers

Y2 - 22 May 1989 through 25 May 1989

ER -