Nitride-sandwiched-oxide gate insulator for low power CMOS

D. Ishikawa; S. Sakai; K. Katsuyama; A. Hiraiwa

Nitride-sandwiched-oxide gate insulator for low power CMOS

D. Ishikawa^*, S. Sakai, K. Katsuyama, A. Hiraiwa

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

A gate insulator with a novel nitride-sandwiched oxide (NSO) structure was formed by successive NO and plasma nitridation steps. This approach reduced the leakage current to 15% of the oxide value, while enhancing the electron mobility by 15%. NSO also has high dielectric reliability and almost completely blocks B penetration in a PMOS device. Our experiments have confirmed that NSO is a very promising technology for forming gate insulators in low-power CMOS devices in the 100-nm to 80-nm node.

Original language	English
Title of host publication	Technical Digest - International Electron Devices Meeting
Pages	869-872
Number of pages	4
Publication status	Published - 2002
Externally published	Yes
Event	2002 IEEE International Devices Meeting (IEDM) - San Francisco, CA, United States Duration: 2002 Dec 8 → 2002 Dec 11

Other

Other	2002 IEEE International Devices Meeting (IEDM)
Country/Territory	United States
City	San Francisco, CA
Period	02/12/8 → 02/12/11

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Nitride-sandwiched-oxide gate insulator for low power CMOS",

abstract = "A gate insulator with a novel nitride-sandwiched oxide (NSO) structure was formed by successive NO and plasma nitridation steps. This approach reduced the leakage current to 15% of the oxide value, while enhancing the electron mobility by 15%. NSO also has high dielectric reliability and almost completely blocks B penetration in a PMOS device. Our experiments have confirmed that NSO is a very promising technology for forming gate insulators in low-power CMOS devices in the 100-nm to 80-nm node.",

author = "D. Ishikawa and S. Sakai and K. Katsuyama and A. Hiraiwa",

year = "2002",

language = "English",

pages = "869--872",

booktitle = "Technical Digest - International Electron Devices Meeting",

note = "2002 IEEE International Devices Meeting (IEDM) ; Conference date: 08-12-2002 Through 11-12-2002",

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TY - GEN

T1 - Nitride-sandwiched-oxide gate insulator for low power CMOS

AU - Ishikawa, D.

AU - Sakai, S.

AU - Katsuyama, K.

AU - Hiraiwa, A.

PY - 2002

Y1 - 2002

N2 - A gate insulator with a novel nitride-sandwiched oxide (NSO) structure was formed by successive NO and plasma nitridation steps. This approach reduced the leakage current to 15% of the oxide value, while enhancing the electron mobility by 15%. NSO also has high dielectric reliability and almost completely blocks B penetration in a PMOS device. Our experiments have confirmed that NSO is a very promising technology for forming gate insulators in low-power CMOS devices in the 100-nm to 80-nm node.

AB - A gate insulator with a novel nitride-sandwiched oxide (NSO) structure was formed by successive NO and plasma nitridation steps. This approach reduced the leakage current to 15% of the oxide value, while enhancing the electron mobility by 15%. NSO also has high dielectric reliability and almost completely blocks B penetration in a PMOS device. Our experiments have confirmed that NSO is a very promising technology for forming gate insulators in low-power CMOS devices in the 100-nm to 80-nm node.

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M3 - Conference contribution

AN - SCOPUS:0036923769

SP - 869

EP - 872

BT - Technical Digest - International Electron Devices Meeting

T2 - 2002 IEEE International Devices Meeting (IEDM)

Y2 - 8 December 2002 through 11 December 2002

ER -

Nitride-sandwiched-oxide gate insulator for low power CMOS

Abstract

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ASJC Scopus subject areas

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