Nitride-sandwiched-oxide gate insulator for low power CMOS

D. Ishikawa*, S. Sakai, K. Katsuyama, A. Hiraiwa

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)


A gate insulator with a novel nitride-sandwiched oxide (NSO) structure was formed by successive NO and plasma nitridation steps. This approach reduced the leakage current to 15% of the oxide value, while enhancing the electron mobility by 15%. NSO also has high dielectric reliability and almost completely blocks B penetration in a PMOS device. Our experiments have confirmed that NSO is a very promising technology for forming gate insulators in low-power CMOS devices in the 100-nm to 80-nm node.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting
Number of pages4
Publication statusPublished - 2002
Externally publishedYes
Event2002 IEEE International Devices Meeting (IEDM) - San Francisco, CA, United States
Duration: 2002 Dec 82002 Dec 11


Other2002 IEEE International Devices Meeting (IEDM)
Country/TerritoryUnited States
CitySan Francisco, CA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Nitride-sandwiched-oxide gate insulator for low power CMOS'. Together they form a unique fingerprint.

Cite this