NMOS OPERATIONAL AMPLIFIER FOR AN OUTPUT BUFFER OF ANALOG LSI's.

Gensuke Goto, Shigeru Fujii, Tetsuo Nakamura, Toshitaka Tsuda, Shigenori Baba

    Research output: Contribution to journalArticle

    Abstract

    An NMOS operational amplifier suitable for a buffer of analog LSI's is reported. It contains three gain stages to achieve the overall gain of 70 db and a buffer stage of drive a capacitance of 200 pf. A monolithic NMOS 10-bit D/A converter including this amplifier as an output buffer has exhibited 10-bit absolute linearity.

    Original languageEnglish
    Pages (from-to)948-951
    Number of pages4
    JournalIEEE Journal of Solid-State Circuits
    VolumeSC-17
    Issue number5
    Publication statusPublished - 1982 Oct

    Fingerprint

    Operational amplifiers
    Capacitance

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Goto, G., Fujii, S., Nakamura, T., Tsuda, T., & Baba, S. (1982). NMOS OPERATIONAL AMPLIFIER FOR AN OUTPUT BUFFER OF ANALOG LSI's. IEEE Journal of Solid-State Circuits, SC-17(5), 948-951.

    NMOS OPERATIONAL AMPLIFIER FOR AN OUTPUT BUFFER OF ANALOG LSI's. / Goto, Gensuke; Fujii, Shigeru; Nakamura, Tetsuo; Tsuda, Toshitaka; Baba, Shigenori.

    In: IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 5, 10.1982, p. 948-951.

    Research output: Contribution to journalArticle

    Goto, G, Fujii, S, Nakamura, T, Tsuda, T & Baba, S 1982, 'NMOS OPERATIONAL AMPLIFIER FOR AN OUTPUT BUFFER OF ANALOG LSI's.', IEEE Journal of Solid-State Circuits, vol. SC-17, no. 5, pp. 948-951.
    Goto G, Fujii S, Nakamura T, Tsuda T, Baba S. NMOS OPERATIONAL AMPLIFIER FOR AN OUTPUT BUFFER OF ANALOG LSI's. IEEE Journal of Solid-State Circuits. 1982 Oct;SC-17(5):948-951.
    Goto, Gensuke ; Fujii, Shigeru ; Nakamura, Tetsuo ; Tsuda, Toshitaka ; Baba, Shigenori. / NMOS OPERATIONAL AMPLIFIER FOR AN OUTPUT BUFFER OF ANALOG LSI's. In: IEEE Journal of Solid-State Circuits. 1982 ; Vol. SC-17, No. 5. pp. 948-951.
    @article{33bd883cfd474c48941f087ac5151435,
    title = "NMOS OPERATIONAL AMPLIFIER FOR AN OUTPUT BUFFER OF ANALOG LSI's.",
    abstract = "An NMOS operational amplifier suitable for a buffer of analog LSI's is reported. It contains three gain stages to achieve the overall gain of 70 db and a buffer stage of drive a capacitance of 200 pf. A monolithic NMOS 10-bit D/A converter including this amplifier as an output buffer has exhibited 10-bit absolute linearity.",
    author = "Gensuke Goto and Shigeru Fujii and Tetsuo Nakamura and Toshitaka Tsuda and Shigenori Baba",
    year = "1982",
    month = "10",
    language = "English",
    volume = "SC-17",
    pages = "948--951",
    journal = "IEEE Journal of Solid-State Circuits",
    issn = "0018-9200",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",
    number = "5",

    }

    TY - JOUR

    T1 - NMOS OPERATIONAL AMPLIFIER FOR AN OUTPUT BUFFER OF ANALOG LSI's.

    AU - Goto, Gensuke

    AU - Fujii, Shigeru

    AU - Nakamura, Tetsuo

    AU - Tsuda, Toshitaka

    AU - Baba, Shigenori

    PY - 1982/10

    Y1 - 1982/10

    N2 - An NMOS operational amplifier suitable for a buffer of analog LSI's is reported. It contains three gain stages to achieve the overall gain of 70 db and a buffer stage of drive a capacitance of 200 pf. A monolithic NMOS 10-bit D/A converter including this amplifier as an output buffer has exhibited 10-bit absolute linearity.

    AB - An NMOS operational amplifier suitable for a buffer of analog LSI's is reported. It contains three gain stages to achieve the overall gain of 70 db and a buffer stage of drive a capacitance of 200 pf. A monolithic NMOS 10-bit D/A converter including this amplifier as an output buffer has exhibited 10-bit absolute linearity.

    UR - http://www.scopus.com/inward/record.url?scp=0020193752&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0020193752&partnerID=8YFLogxK

    M3 - Article

    VL - SC-17

    SP - 948

    EP - 951

    JO - IEEE Journal of Solid-State Circuits

    JF - IEEE Journal of Solid-State Circuits

    SN - 0018-9200

    IS - 5

    ER -