Novel and efficient min cut based voltage assignment in gate level

Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this paper, we propose a novel min cut based algorithm for multiple supply voltage assignment under timing constraints. Different with the traditional sensitivity based methods which focus on how to make full use of the slacks of non-critical gates, the proposed algorithm concentrates on critical gates. The circuit is initialized in the lowest power level, then the length of critical paths is tried to be shortened with the minimized power increment until the timing constraints are satisfied. Experimental results show that given dual-vdd, our method beats traditional methods both in power saving and runtime, especially runtime.

Original languageEnglish
Title of host publicationProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages150-155
Number of pages6
DOIs
Publication statusPublished - 2011
Event12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA
Duration: 2011 Mar 142011 Mar 16

Other

Other12th International Symposium on Quality Electronic Design, ISQED 2011
CitySanta Clara, CA
Period11/3/1411/3/16

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Lin, T., Dong, S., Chen, S., Ma, Y., He, O., & Goto, S. (2011). Novel and efficient min cut based voltage assignment in gate level. In Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011 (pp. 150-155). [5770719] https://doi.org/10.1109/ISQED.2011.5770719