Novel double well with buffer N- and P+ gettering layers for suppression of soft error rate (DOWNSER)

S. Komori; T. Yamashita; T. Kuroi; M. Inuishi; N. Tsubouchi

Novel double well with buffer N^- and P⁺ gettering layers for suppression of soft error rate (DOWNSER)

S. Komori, T. Yamashita, T. Kuroi, M. Inuishi, N. Tsubouchi

Research output: Contribution to journal › Conference article › peer-review

Abstract

A novel double well with buffer n^- and gettering layers structure for strong suppression of SER (DOWNSER) is briefly presented in this paper. The mechanisms for reduction of SER have been investigated by experimental and simulation studies. The buffer n^- and the gettering layer in DOWNSER structure play the important role in cutting off the minority carrier generated from the incident alpha particle in the p-type region or the reverse biased junction.

Original language	English
Pages (from-to)	41-42
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
Publication status	Published - 1994 Dec 1
Externally published	Yes
Event	Proceedings of the 1994 Symposium on VLSI Technology - Honolulu, HI, USA Duration: 1994 Jun 7 → 1994 Jun 9

ASJC Scopus subject areas

Electrical and Electronic Engineering

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@article{48f89fdbd59944daae751f4c8d2a861b,

title = "Novel double well with buffer N- and P+ gettering layers for suppression of soft error rate (DOWNSER)",

abstract = "A novel double well with buffer n- and gettering layers structure for strong suppression of SER (DOWNSER) is briefly presented in this paper. The mechanisms for reduction of SER have been investigated by experimental and simulation studies. The buffer n- and the gettering layer in DOWNSER structure play the important role in cutting off the minority carrier generated from the incident alpha particle in the p-type region or the reverse biased junction.",

author = "S. Komori and T. Yamashita and T. Kuroi and M. Inuishi and N. Tsubouchi",

year = "1994",

month = dec,

day = "1",

language = "English",

pages = "41--42",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1994 Symposium on VLSI Technology ; Conference date: 07-06-1994 Through 09-06-1994",

}

TY - JOUR

T1 - Novel double well with buffer N- and P+ gettering layers for suppression of soft error rate (DOWNSER)

AU - Komori, S.

AU - Yamashita, T.

AU - Kuroi, T.

AU - Inuishi, M.

AU - Tsubouchi, N.

PY - 1994/12/1

Y1 - 1994/12/1

N2 - A novel double well with buffer n- and gettering layers structure for strong suppression of SER (DOWNSER) is briefly presented in this paper. The mechanisms for reduction of SER have been investigated by experimental and simulation studies. The buffer n- and the gettering layer in DOWNSER structure play the important role in cutting off the minority carrier generated from the incident alpha particle in the p-type region or the reverse biased junction.

AB - A novel double well with buffer n- and gettering layers structure for strong suppression of SER (DOWNSER) is briefly presented in this paper. The mechanisms for reduction of SER have been investigated by experimental and simulation studies. The buffer n- and the gettering layer in DOWNSER structure play the important role in cutting off the minority carrier generated from the incident alpha particle in the p-type region or the reverse biased junction.

UR - http://www.scopus.com/inward/record.url?scp=0028600435&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028600435&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0028600435

SP - 41

EP - 42

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

SN - 0743-1562

T2 - Proceedings of the 1994 Symposium on VLSI Technology

Y2 - 7 June 1994 through 9 June 1994

ER -