On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit

H. Notani, M. Fujii, H. Suzuki, H. Makino, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

An on-chip digital Ids measurement method is proposed in this report. In the proposed method, Ids is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS Ids (I dn) and PMOS Ids (Idp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first Ids calculated from measured frequencies, and the second Ids directly measured for reference, was analyzed. The standard deviations of the mismatch error in Idn and Idp are 1.64% and 1.09%, respectively. The margin of 3σ is within 5% which is our target tolerance for a practical application.

Original languageEnglish
Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages405-408
Number of pages4
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
Duration: 2008 Nov 32008 Nov 5

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
CountryJapan
CityFukuoka
Period08/11/308/11/5

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Notani, H., Fujii, M., Suzuki, H., Makino, H., & Shinohara, H. (2008). On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (pp. 405-408). [4708813] https://doi.org/10.1109/ASSCC.2008.4708813