On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit

H. Notani; M. Fujii; H. Suzuki; H. Makino; H. Shinohara

doi:10.1109/ASSCC.2008.4708813

On-chip digital I_dn and I_dp measurement by 65 nm CMOS speed monitor circuit

H. Notani^*, M. Fujii, H. Suzuki, H. Makino, H. Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

An on-chip digital I_ds measurement method is proposed in this report. In the proposed method, I_ds is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS I_ds (I _dn) and PMOS I_ds (I_dp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first Ids calculated from measured frequencies, and the second I_ds directly measured for reference, was analyzed. The standard deviations of the mismatch error in I_dn and I_dp are 1.64% and 1.09%, respectively. The margin of 3σ is within 5% which is our target tolerance for a practical application.

Original language	English
Title of host publication	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages	405-408
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2008.4708813
Publication status	Published - 2008 Dec 1
Externally published	Yes
Event	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan Duration: 2008 Nov 3 → 2008 Nov 5

Publication series

Name	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Country/Territory	Japan
City	Fukuoka
Period	08/11/3 → 08/11/5

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2008.4708813

Cite this

Notani, H., Fujii, M., Suzuki, H., Makino, H., & Shinohara, H. (2008). On-chip digital I_dn and I_dp measurement by 65 nm CMOS speed monitor circuit. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (pp. 405-408). [4708813] (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008). https://doi.org/10.1109/ASSCC.2008.4708813

On-chip digital I_dn and I_dp measurement by 65 nm CMOS speed monitor circuit. / Notani, H.; Fujii, M.; Suzuki, H. et al.

Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008. 2008. p. 405-408 4708813 (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Notani, H, Fujii, M, Suzuki, H, Makino, H & Shinohara, H 2008, On-chip digital I_dn and I_dp measurement by 65 nm CMOS speed monitor circuit. in Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008., 4708813, Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp. 405-408, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, Fukuoka, Japan, 08/11/3. https://doi.org/10.1109/ASSCC.2008.4708813

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abstract = "An on-chip digital Ids measurement method is proposed in this report. In the proposed method, Ids is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS Ids (I dn) and PMOS Ids (Idp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first Ids calculated from measured frequencies, and the second Ids directly measured for reference, was analyzed. The standard deviations of the mismatch error in Idn and Idp are 1.64% and 1.09%, respectively. The margin of 3σ is within 5% which is our target tolerance for a practical application.",

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