TY - GEN
T1 - On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit
AU - Notani, H.
AU - Fujii, M.
AU - Suzuki, H.
AU - Makino, H.
AU - Shinohara, H.
PY - 2008/12/1
Y1 - 2008/12/1
N2 - An on-chip digital Ids measurement method is proposed in this report. In the proposed method, Ids is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS Ids (I dn) and PMOS Ids (Idp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first Ids calculated from measured frequencies, and the second Ids directly measured for reference, was analyzed. The standard deviations of the mismatch error in Idn and Idp are 1.64% and 1.09%, respectively. The margin of 3σ is within 5% which is our target tolerance for a practical application.
AB - An on-chip digital Ids measurement method is proposed in this report. In the proposed method, Ids is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS Ids (I dn) and PMOS Ids (Idp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first Ids calculated from measured frequencies, and the second Ids directly measured for reference, was analyzed. The standard deviations of the mismatch error in Idn and Idp are 1.64% and 1.09%, respectively. The margin of 3σ is within 5% which is our target tolerance for a practical application.
UR - http://www.scopus.com/inward/record.url?scp=67649961643&partnerID=8YFLogxK
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U2 - 10.1109/ASSCC.2008.4708813
DO - 10.1109/ASSCC.2008.4708813
M3 - Conference contribution
AN - SCOPUS:67649961643
SN - 9781424426058
T3 - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
SP - 405
EP - 408
BT - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
T2 - 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Y2 - 3 November 2008 through 5 November 2008
ER -