On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

M. Fujii, H. Suzuki, H. Notani, H. Makino, H. Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper proposes on-chip leakage monitor circuit to scan optimal reversed body-biasing voltage (VBB) at which leakage current becomes minimal under gate induced drain leakage (GIDL) effect. The proposed circuit determines optimal VBB from the differential measurement of two replica circuit without absolute leakage current measurement. We fabricated this leakage monitor circuit in a 45nm-CMOS process. Measurement results shows 0.1 V resolution of VBB optimization.

Original languageEnglish
Title of host publicationESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference
Pages258-261
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 31
Event34th European Solid-State Circuits Conference, ESSCIRC 2008 - Edinburgh, Scotland, United Kingdom
Duration: 2008 Sep 152008 Sep 19

Publication series

NameESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Other

Other34th European Solid-State Circuits Conference, ESSCIRC 2008
CountryUnited Kingdom
CityEdinburgh, Scotland
Period08/9/1508/9/19

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Fujii, M., Suzuki, H., Notani, H., Makino, H., & Shinohara, H. (2008). On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. In ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference (pp. 258-261). [4681841] (ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2008.4681841