On-chip multibit-test scheme for VLSI memories

Hideto Hidaka, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Yasumasa Nishimura, Tsutomu Yoshihara

Research output: Contribution to journalArticle

Abstract

To reduce the time needed for testing VLSI memory chips, an on-chip multibit-test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1-Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256-K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one-half to one-third.

Original languageEnglish
Pages (from-to)78-87
Number of pages10
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume71
Issue number9
Publication statusPublished - 1988 Sep
Externally publishedYes

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very large scale integration
chips
Data storage equipment
Dynamic random access storage
Testing
Redundancy
Electric power utilization
redundancy

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hidaka, H., Fujishima, K., Kumanoya, M., Miyatake, H., Dosaka, K., Nishimura, Y., & Yoshihara, T. (1988). On-chip multibit-test scheme for VLSI memories. Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), 71(9), 78-87.

On-chip multibit-test scheme for VLSI memories. / Hidaka, Hideto; Fujishima, Kazuyasu; Kumanoya, Masaki; Miyatake, Hideshi; Dosaka, Katsumi; Nishimura, Yasumasa; Yoshihara, Tsutomu.

In: Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), Vol. 71, No. 9, 09.1988, p. 78-87.

Research output: Contribution to journalArticle

Hidaka, H, Fujishima, K, Kumanoya, M, Miyatake, H, Dosaka, K, Nishimura, Y & Yoshihara, T 1988, 'On-chip multibit-test scheme for VLSI memories', Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), vol. 71, no. 9, pp. 78-87.
Hidaka, Hideto ; Fujishima, Kazuyasu ; Kumanoya, Masaki ; Miyatake, Hideshi ; Dosaka, Katsumi ; Nishimura, Yasumasa ; Yoshihara, Tsutomu. / On-chip multibit-test scheme for VLSI memories. In: Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi). 1988 ; Vol. 71, No. 9. pp. 78-87.
@article{f1606bc3394f4a25b459ebcf5c202f0c,
title = "On-chip multibit-test scheme for VLSI memories",
abstract = "To reduce the time needed for testing VLSI memory chips, an on-chip multibit-test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1-Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256-K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one-half to one-third.",
author = "Hideto Hidaka and Kazuyasu Fujishima and Masaki Kumanoya and Hideshi Miyatake and Katsumi Dosaka and Yasumasa Nishimura and Tsutomu Yoshihara",
year = "1988",
month = "9",
language = "English",
volume = "71",
pages = "78--87",
journal = "Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)",
issn = "8756-663X",
publisher = "Scripta Technica",
number = "9",

}

TY - JOUR

T1 - On-chip multibit-test scheme for VLSI memories

AU - Hidaka, Hideto

AU - Fujishima, Kazuyasu

AU - Kumanoya, Masaki

AU - Miyatake, Hideshi

AU - Dosaka, Katsumi

AU - Nishimura, Yasumasa

AU - Yoshihara, Tsutomu

PY - 1988/9

Y1 - 1988/9

N2 - To reduce the time needed for testing VLSI memory chips, an on-chip multibit-test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1-Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256-K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one-half to one-third.

AB - To reduce the time needed for testing VLSI memory chips, an on-chip multibit-test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1-Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256-K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one-half to one-third.

UR - http://www.scopus.com/inward/record.url?scp=0024071670&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024071670&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0024071670

VL - 71

SP - 78

EP - 87

JO - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)

JF - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)

SN - 8756-663X

IS - 9

ER -