ON THE DESIGN OF A HIGH-PERFORMANCE LSI CIRCUIT DIGITAL SIGNAL PROCESSOR FOR COMMUNICATION.

Hirohisa Gambe, Toshi Ikezawa, Toshihiko Matsumura, Toshitaka Tsuda, Shigeru Fujii

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    Abstract

    This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0. 6 mu s per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are shown. These examples illustrate the high efficiency of the developed DSP device.

    Original languageEnglish
    Pages (from-to)357-368
    Number of pages12
    JournalIEEE Journal on Selected Areas in Communications
    VolumeSAC-3
    Issue number2
    Publication statusPublished - 1985 Mar

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    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Electrical and Electronic Engineering

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