On the number of 3-D IC floorplan configurations and a solution perturbation method with good convergence

Song Chen; Takeshi Yoshimura

doi:10.1109/APCCAS.2006.342203

On the number of 3-D IC floorplan configurations and a solution perturbation method with good convergence

Song Chen^*, Takeshi Yoshimura

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

3-D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3-D IC floorplanning. It is proved that the number of configuration of 3-D floorplans is less than that of planar floorplans. Sequence Pair is extended (P-SP) to represent 3-D IC floorplans. A new solution perturbation method Remove and Insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method.

Original language	English
Title of host publication	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages	1867-1870
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342203
Publication status	Published - 2006
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - Duration: 2006 Dec 4 → 2006 Dec 6

Other

Other	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Period	06/12/4 → 06/12/6

Keywords

3-D
Floorplanning
Sequence pair
VLSI

ASJC Scopus subject areas

Engineering(all)

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10.1109/APCCAS.2006.342203

Cite this

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title = "On the number of 3-D IC floorplan configurations and a solution perturbation method with good convergence",

abstract = "3-D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3-D IC floorplanning. It is proved that the number of configuration of 3-D floorplans is less than that of planar floorplans. Sequence Pair is extended (P-SP) to represent 3-D IC floorplans. A new solution perturbation method Remove and Insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method.",

keywords = "3-D, Floorplanning, Sequence pair, VLSI",

author = "Song Chen and Takeshi Yoshimura",

year = "2006",

doi = "10.1109/APCCAS.2006.342203",

language = "English",

isbn = "1424403871",

pages = "1867--1870",

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note = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 04-12-2006 Through 06-12-2006",

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TY - GEN

T1 - On the number of 3-D IC floorplan configurations and a solution perturbation method with good convergence

AU - Chen, Song

AU - Yoshimura, Takeshi

PY - 2006

Y1 - 2006

N2 - 3-D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3-D IC floorplanning. It is proved that the number of configuration of 3-D floorplans is less than that of planar floorplans. Sequence Pair is extended (P-SP) to represent 3-D IC floorplans. A new solution perturbation method Remove and Insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method.

AB - 3-D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3-D IC floorplanning. It is proved that the number of configuration of 3-D floorplans is less than that of planar floorplans. Sequence Pair is extended (P-SP) to represent 3-D IC floorplans. A new solution perturbation method Remove and Insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method.

KW - 3-D

KW - Floorplanning

KW - Sequence pair

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=50249169821&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50249169821&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2006.342203

DO - 10.1109/APCCAS.2006.342203

M3 - Conference contribution

AN - SCOPUS:50249169821

SN - 1424403871

SN - 9781424403875

SP - 1867

EP - 1870

BT - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 4 December 2006 through 6 December 2006

ER -

On the number of 3-D IC floorplan configurations and a solution perturbation method with good convergence

Abstract

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Keywords

ASJC Scopus subject areas

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