Optimization of area and power in multi-mode power gating scheme for static memory elements

Xing Su, Shinji Kimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an optimization method of area and power for static memory elements by using multi-mode power gating (MMPG) scheme. A 2-transistor MMPG scheme replaces the usual 5-transistor one to effectively reduce on chip area overhead and leakage power, simultaneously combining trimming circuits (TC) to guarantee the safety of data retention. When applying the proposed approach into clean/dirty-cache (CD-cache), we can reduce area overhead and leakage power consumption. The simulation results show that the area overhead of SRAM with the proposed approach is reduced from 33.4% to 21.8% compared to that of SRAM with usual MMPG. On the other hand, leakage power is reduced by 12.35% compared to SRAM with usual MMPG and by 86.77% compared to SRAM without power gating scheme. Moreover, the ability of noise immunity of SRAM with proposed approach can also be improved.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages214-217
Number of pages4
ISBN (Electronic)9781509015702
DOIs
Publication statusPublished - 2017 Jan 3
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 252016 Oct 28

Other

Other2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period16/10/2516/10/28

Fingerprint

Static random access storage
Data storage equipment
Transistors
Trimming
Electric power utilization
Networks (circuits)

Keywords

  • area overhead
  • Clean/Dirty-cache
  • leakage power
  • multi-mode power gating
  • trimming circuits

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing

Cite this

Su, X., & Kimura, S. (2017). Optimization of area and power in multi-mode power gating scheme for static memory elements. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 214-217). [7803936] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7803936

Optimization of area and power in multi-mode power gating scheme for static memory elements. / Su, Xing; Kimura, Shinji.

2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 214-217 7803936.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Su, X & Kimura, S 2017, Optimization of area and power in multi-mode power gating scheme for static memory elements. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7803936, Institute of Electrical and Electronics Engineers Inc., pp. 214-217, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Korea, Republic of, 16/10/25. https://doi.org/10.1109/APCCAS.2016.7803936
Su X, Kimura S. Optimization of area and power in multi-mode power gating scheme for static memory elements. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 214-217. 7803936 https://doi.org/10.1109/APCCAS.2016.7803936
Su, Xing ; Kimura, Shinji. / Optimization of area and power in multi-mode power gating scheme for static memory elements. 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 214-217
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