Optimized design for high-performance megabit DRAMs

Masaki Kumanoya; Katsumi Dosaka; Yashuhiro Konishi; Tsutomu Yoshihara; Hideshi Miyatake; Yuto Ikeda; Isao Furuta

Optimized design for high-performance megabit DRAMs

Masaki Kumanoya^*, Katsumi Dosaka, Yashuhiro Konishi, Tsutomu Yoshihara, Hideshi Miyatake, Yuto Ikeda, Isao Furuta

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (t_c = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.

Original language	English
Pages (from-to)	14-23
Number of pages	10
Journal	Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume	72
Issue number	8
Publication status	Published - 1989 Aug
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Optimized design for high-performance megabit DRAMs",

abstract = "Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.",

author = "Masaki Kumanoya and Katsumi Dosaka and Yashuhiro Konishi and Tsutomu Yoshihara and Hideshi Miyatake and Yuto Ikeda and Isao Furuta",

year = "1989",

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language = "English",

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journal = "Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)",

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AU - Kumanoya, Masaki

AU - Dosaka, Katsumi

AU - Konishi, Yashuhiro

AU - Yoshihara, Tsutomu

AU - Miyatake, Hideshi

AU - Ikeda, Yuto

AU - Furuta, Isao

PY - 1989/8

Y1 - 1989/8

N2 - Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.

AB - Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.

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Optimized design for high-performance megabit DRAMs

Abstract

ASJC Scopus subject areas

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