Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.
|Number of pages||10|
|Journal||Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)|
|Publication status||Published - 1989 Aug|
ASJC Scopus subject areas
- Electrical and Electronic Engineering