OSCAR Parallelizing and Power Reducing Compiler and API for Heterogeneous Multicores: (Invited Paper)

Hironori Kasahara, Keiji Kimura, Toshiaki Kitamura, Hiroki Mikami, Kazutaka Morita, Kazuki Fujita, Kazuki Yamamoto, Tohma Kawasumi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Heterogeneous computing systems, connecting general-purpose processor cores with accelerators and/or different kinds of general-purpose processor cores, have been widely used for HPC, cloud servers, self-driving vehicles, AI robots, and so on. They are used to obtain high performance and/or low power consumption. This paper introduces the OSCAR (Optimally Scheduled Advanced Multiprocessor) parallelizing compiler and OSCAR API. They allow users to automatically parallelize and power-reduce a C or Fortran program for various heterogeneous computing systems. OSCAR compiler has been developed since 1983, aiming at co-design of multiprocessor architecture and compiler. Currently, it can generate parallel machine codes for any shared memory homogeneous and heterogeneous multicores with or without hardware cache-coherent mechanism if a sequential C or Fortran compiler exists for the target multicore. OSCAR compiler translates a sequential user program written in C or Fortran into a parallelized C or Fortran program with OSCAR API compatible with frequency-voltage control, clock-gating, and power gating directives for each core, memory module, and interconnect defined in OSCAR API. The generated parallel program consists of threads specified by OpenMP "section"directives. The threads can be compiled into machine codes by an OpenMP compiler or a sequential C or Fortran compiler for a target general-purpose processor cores or accelerator cores. The compilation flow and execution and power-reduce performance for scientific and embedded applications and Deep Learning are shown on several heterogeneous systems, such as a heterogeneous multicore processor having eight general-purpose cores and 4 DRPs, or Dynamically Reconfigurable Processors, a heterogeneous multicore on FPGA using NIOS cores, and a new vector accelerator based on the past Japanese supercomputers and a personal vector supercomputer NEC Aurora Tsubasa.

Original languageEnglish
Title of host publicationProceedings of PEHC 2021
Subtitle of host publicationWorkshop on Programming Environments for Heterogeneous Computing, Held in conjunction with SC 2021: The International Conference for High Performance Computing, Networking, Storage and Analysis
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages10-19
Number of pages10
ISBN (Electronic)9781728186764
DOIs
Publication statusPublished - 2021
Event2021 IEEE/ACM Workshop on Programming Environments for Heterogeneous Computing, PEHC 2021 - St. Louis, United States
Duration: 2021 Nov 19 → …

Publication series

NameProceedings of PEHC 2021: Workshop on Programming Environments for Heterogeneous Computing, Held in conjunction with SC 2021: The International Conference for High Performance Computing, Networking, Storage and Analysis

Conference

Conference2021 IEEE/ACM Workshop on Programming Environments for Heterogeneous Computing, PEHC 2021
Country/TerritoryUnited States
CitySt. Louis
Period21/11/19 → …

Keywords

  • accelerator
  • heterogeneous multicore
  • paralelizing compiler

ASJC Scopus subject areas

  • Artificial Intelligence
  • Hardware and Architecture
  • Software

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