Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory

Yoshikazu Miyawaki; Takeshi Nakayama; Masaaki Mihara; Shinji Kawai; Minoru Ohkawa; Natsuo Ajika; Masahiro Hatanaka; Yasushi Terada; Tsutomu Yoshihara

Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory

Yoshikazu Miyawaki^*, Takeshi Nakayama, Masaaki Mihara, Shinji Kawai, Minoru Ohkawa, Natsuo Ajika, Masahiro Hatanaka, Yasushi Terada, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The paper presents an over erasure detection technique. The source line bias scheme in the erase sequence extends the lower limit of threshold voltage detection. With the use of the overerase recover programming, a very tight distribution of the erased state threshold voltage can be obtained without the utilization of a negative voltage. This technique can become one of the key techniques for future generation low voltage flash memories.

Original language	English
Title of host publication	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Place of Publication	Piscataway, NJ, United States
Publisher	IEEE
Pages	63-64
Number of pages	2
Publication status	Published - 1994
Externally published	Yes
Event	Proceedings of the 1994 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 1994 Jun 9 → 1994 Jun 11

Other

Other	Proceedings of the 1994 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	94/6/9 → 94/6/11

ASJC Scopus subject areas

Engineering(all)

Cite this

Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory. / Miyawaki, Yoshikazu; Nakayama, Takeshi; Mihara, Masaaki; Kawai, Shinji; Ohkawa, Minoru; Ajika, Natsuo; Hatanaka, Masahiro; Terada, Yasushi; Yoshihara, Tsutomu.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Piscataway, NJ, United States : IEEE, 1994. p. 63-64.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Miyawaki, Y, Nakayama, T, Mihara, M, Kawai, S, Ohkawa, M, Ajika, N, Hatanaka, M, Terada, Y & Yoshihara, T 1994, Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers. IEEE, Piscataway, NJ, United States, pp. 63-64, Proceedings of the 1994 Symposium on VLSI Circuits, Honolulu, HI, USA, 94/6/9.

Miyawaki, Yoshikazu ; Nakayama, Takeshi ; Mihara, Masaaki ; Kawai, Shinji ; Ohkawa, Minoru ; Ajika, Natsuo ; Hatanaka, Masahiro ; Terada, Yasushi ; Yoshihara, Tsutomu. / Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Piscataway, NJ, United States : IEEE, 1994. pp. 63-64

@inproceedings{193f5ef81a244d5d8be11ccb0ca02807,

title = "Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory",

abstract = "The paper presents an over erasure detection technique. The source line bias scheme in the erase sequence extends the lower limit of threshold voltage detection. With the use of the overerase recover programming, a very tight distribution of the erased state threshold voltage can be obtained without the utilization of a negative voltage. This technique can become one of the key techniques for future generation low voltage flash memories.",

author = "Yoshikazu Miyawaki and Takeshi Nakayama and Masaaki Mihara and Shinji Kawai and Minoru Ohkawa and Natsuo Ajika and Masahiro Hatanaka and Yasushi Terada and Tsutomu Yoshihara",

year = "1994",

language = "English",

pages = "63--64",

booktitle = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "IEEE",

note = "Proceedings of the 1994 Symposium on VLSI Circuits ; Conference date: 09-06-1994 Through 11-06-1994",

}

TY - GEN

T1 - Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory

AU - Miyawaki, Yoshikazu

AU - Nakayama, Takeshi

AU - Mihara, Masaaki

AU - Kawai, Shinji

AU - Ohkawa, Minoru

AU - Ajika, Natsuo

AU - Hatanaka, Masahiro

AU - Terada, Yasushi

AU - Yoshihara, Tsutomu

PY - 1994

Y1 - 1994

N2 - The paper presents an over erasure detection technique. The source line bias scheme in the erase sequence extends the lower limit of threshold voltage detection. With the use of the overerase recover programming, a very tight distribution of the erased state threshold voltage can be obtained without the utilization of a negative voltage. This technique can become one of the key techniques for future generation low voltage flash memories.

AB - The paper presents an over erasure detection technique. The source line bias scheme in the erase sequence extends the lower limit of threshold voltage detection. With the use of the overerase recover programming, a very tight distribution of the erased state threshold voltage can be obtained without the utilization of a negative voltage. This technique can become one of the key techniques for future generation low voltage flash memories.

UR - http://www.scopus.com/inward/record.url?scp=0028574973&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028574973&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0028574973

SP - 63

EP - 64

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

PB - IEEE

CY - Piscataway, NJ, United States

T2 - Proceedings of the 1994 Symposium on VLSI Circuits

Y2 - 9 June 1994 through 11 June 1994

ER -

Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory

Abstract

Other

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this