Abstract
The paper presents an over erasure detection technique. The source line bias scheme in the erase sequence extends the lower limit of threshold voltage detection. With the use of the overerase recover programming, a very tight distribution of the erased state threshold voltage can be obtained without the utilization of a negative voltage. This technique can become one of the key techniques for future generation low voltage flash memories.
| Original language | English |
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| Title of host publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | IEEE |
| Pages | 63-64 |
| Number of pages | 2 |
| Publication status | Published - 1994 |
| Externally published | Yes |
| Event | Proceedings of the 1994 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 1994 Jun 9 → 1994 Jun 11 |
Other
| Other | Proceedings of the 1994 Symposium on VLSI Circuits |
|---|---|
| City | Honolulu, HI, USA |
| Period | 94/6/9 → 94/6/11 |
ASJC Scopus subject areas
- Engineering(all)
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Cite this
Miyawaki, Y., Nakayama, T., Mihara, M., Kawai, S., Ohkawa, M., Ajika, N., Hatanaka, M., Terada, Y., & Yoshihara, T. (1994). Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 63-64). IEEE.