Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory

Yoshikazu Miyawaki, Takeshi Nakayama, Masaaki Mihara, Shinji Kawai, Minoru Ohkawa, Natsuo Ajika, Masahiro Hatanaka, Yasushi Terada, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The paper presents an over erasure detection technique. The source line bias scheme in the erase sequence extends the lower limit of threshold voltage detection. With the use of the overerase recover programming, a very tight distribution of the erased state threshold voltage can be obtained without the utilization of a negative voltage. This technique can become one of the key techniques for future generation low voltage flash memories.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages63-64
Number of pages2
Publication statusPublished - 1994
Externally publishedYes
EventProceedings of the 1994 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: 1994 Jun 91994 Jun 11

Other

OtherProceedings of the 1994 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period94/6/994/6/11

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Miyawaki, Y., Nakayama, T., Mihara, M., Kawai, S., Ohkawa, M., Ajika, N., Hatanaka, M., Terada, Y., & Yoshihara, T. (1994). Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 63-64). IEEE.