Parallel architecture for high-speed Reed-Solomon codec

T. K. Matsushima, T. Matsushima, S. Hirasawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

This paper presents a parallel architecture for a high-speed Reed-Solomon (RS) encoder and decoder (codec) LSI. Since the architecture allows H symbols to be processed in parallel the codec LSI achieves a data rate of mLH b/s. where m is the symbol size (m bits per symbol), L is the clock frequency of the circuit, and H is an arbitrary integer. As an example, we investigate hardware complexity, delay and critical path length for a (255.251) RS code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with, this parallel architecture is that the encoder's critical path length increases with H, the proposed architectures is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that parallel RS codecs, which can keep up with optical transmission rates, i.e. several giga bits/sec. could be implemented on one LSI chip, using current CMOS technology.

Original languageEnglish
Title of host publicationITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages468-473
Number of pages6
ISBN (Electronic)0780350308, 9780780350304
DOIs
Publication statusPublished - 1998 Jan 1
EventSBT/IEEE International Telecommunications Symposium, ITS 1998 - Sao Paulo, Brazil
Duration: 1998 Aug 91998 Aug 13

Publication series

NameITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium
Volume2

Other

OtherSBT/IEEE International Telecommunications Symposium, ITS 1998
CountryBrazil
CitySao Paulo
Period98/8/998/8/13

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Signal Processing

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