Parallel architecture for high-speed Reed-Solomon codec

T. K. Matsushima, Toshiyasu Matsushima, S. Hirasawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    14 Citations (Scopus)

    Abstract

    This paper presents a parallel architecture for a high-speed Reed-Solomon (RS) encoder and decoder (codec) LSI. Since the architecture allows H symbols to be processed in parallel the codec LSI achieves a data rate of mLH b/s. where m is the symbol size (m bits per symbol), L is the clock frequency of the circuit, and H is an arbitrary integer. As an example, we investigate hardware complexity, delay and critical path length for a (255.251) RS code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with, this parallel architecture is that the encoder's critical path length increases with H, the proposed architectures is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that parallel RS codecs, which can keep up with optical transmission rates, i.e. several giga bits/sec. could be implemented on one LSI chip, using current CMOS technology.

    Original languageEnglish
    Title of host publicationITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages468-473
    Number of pages6
    Volume2
    ISBN (Electronic)0780350308, 9780780350304
    DOIs
    Publication statusPublished - 1998 Jan 1
    EventSBT/IEEE International Telecommunications Symposium, ITS 1998 - Sao Paulo, Brazil
    Duration: 1998 Aug 91998 Aug 13

    Other

    OtherSBT/IEEE International Telecommunications Symposium, ITS 1998
    CountryBrazil
    CitySao Paulo
    Period98/8/998/8/13

    Fingerprint

    Parallel architectures
    Networks (circuits)
    Hardware
    Reed-Solomon codes
    Light transmission
    Clocks

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Signal Processing

    Cite this

    Matsushima, T. K., Matsushima, T., & Hirasawa, S. (1998). Parallel architecture for high-speed Reed-Solomon codec. In ITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium (Vol. 2, pp. 468-473). [718439] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITS.1998.718439

    Parallel architecture for high-speed Reed-Solomon codec. / Matsushima, T. K.; Matsushima, Toshiyasu; Hirasawa, S.

    ITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium. Vol. 2 Institute of Electrical and Electronics Engineers Inc., 1998. p. 468-473 718439.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Matsushima, TK, Matsushima, T & Hirasawa, S 1998, Parallel architecture for high-speed Reed-Solomon codec. in ITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium. vol. 2, 718439, Institute of Electrical and Electronics Engineers Inc., pp. 468-473, SBT/IEEE International Telecommunications Symposium, ITS 1998, Sao Paulo, Brazil, 98/8/9. https://doi.org/10.1109/ITS.1998.718439
    Matsushima TK, Matsushima T, Hirasawa S. Parallel architecture for high-speed Reed-Solomon codec. In ITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium. Vol. 2. Institute of Electrical and Electronics Engineers Inc. 1998. p. 468-473. 718439 https://doi.org/10.1109/ITS.1998.718439
    Matsushima, T. K. ; Matsushima, Toshiyasu ; Hirasawa, S. / Parallel architecture for high-speed Reed-Solomon codec. ITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium. Vol. 2 Institute of Electrical and Electronics Engineers Inc., 1998. pp. 468-473
    @inproceedings{e8cee62d1a4946d69bcb794737fbaaa0,
    title = "Parallel architecture for high-speed Reed-Solomon codec",
    abstract = "This paper presents a parallel architecture for a high-speed Reed-Solomon (RS) encoder and decoder (codec) LSI. Since the architecture allows H symbols to be processed in parallel the codec LSI achieves a data rate of mLH b/s. where m is the symbol size (m bits per symbol), L is the clock frequency of the circuit, and H is an arbitrary integer. As an example, we investigate hardware complexity, delay and critical path length for a (255.251) RS code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with, this parallel architecture is that the encoder's critical path length increases with H, the proposed architectures is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that parallel RS codecs, which can keep up with optical transmission rates, i.e. several giga bits/sec. could be implemented on one LSI chip, using current CMOS technology.",
    author = "Matsushima, {T. K.} and Toshiyasu Matsushima and S. Hirasawa",
    year = "1998",
    month = "1",
    day = "1",
    doi = "10.1109/ITS.1998.718439",
    language = "English",
    volume = "2",
    pages = "468--473",
    booktitle = "ITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",

    }

    TY - GEN

    T1 - Parallel architecture for high-speed Reed-Solomon codec

    AU - Matsushima, T. K.

    AU - Matsushima, Toshiyasu

    AU - Hirasawa, S.

    PY - 1998/1/1

    Y1 - 1998/1/1

    N2 - This paper presents a parallel architecture for a high-speed Reed-Solomon (RS) encoder and decoder (codec) LSI. Since the architecture allows H symbols to be processed in parallel the codec LSI achieves a data rate of mLH b/s. where m is the symbol size (m bits per symbol), L is the clock frequency of the circuit, and H is an arbitrary integer. As an example, we investigate hardware complexity, delay and critical path length for a (255.251) RS code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with, this parallel architecture is that the encoder's critical path length increases with H, the proposed architectures is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that parallel RS codecs, which can keep up with optical transmission rates, i.e. several giga bits/sec. could be implemented on one LSI chip, using current CMOS technology.

    AB - This paper presents a parallel architecture for a high-speed Reed-Solomon (RS) encoder and decoder (codec) LSI. Since the architecture allows H symbols to be processed in parallel the codec LSI achieves a data rate of mLH b/s. where m is the symbol size (m bits per symbol), L is the clock frequency of the circuit, and H is an arbitrary integer. As an example, we investigate hardware complexity, delay and critical path length for a (255.251) RS code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with, this parallel architecture is that the encoder's critical path length increases with H, the proposed architectures is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that parallel RS codecs, which can keep up with optical transmission rates, i.e. several giga bits/sec. could be implemented on one LSI chip, using current CMOS technology.

    UR - http://www.scopus.com/inward/record.url?scp=0009618966&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0009618966&partnerID=8YFLogxK

    U2 - 10.1109/ITS.1998.718439

    DO - 10.1109/ITS.1998.718439

    M3 - Conference contribution

    AN - SCOPUS:0009618966

    VL - 2

    SP - 468

    EP - 473

    BT - ITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium

    PB - Institute of Electrical and Electronics Engineers Inc.

    ER -