Parallel design of control systems utilizing dead time for embedded multicore processors

Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.

Original languageEnglish
Title of host publicationIEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII
PublisherIEEE Computer Society
ISBN (Print)9781479938094
DOIs
Publication statusPublished - 2014
Externally publishedYes
Event17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014 - Yokohama, Japan
Duration: 2014 Apr 142014 Apr 16

Publication series

NameIEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII

Other

Other17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014
Country/TerritoryJapan
CityYokohama
Period14/4/1414/4/16

Keywords

  • control system
  • dead time
  • model based design
  • multicore
  • parallelization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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