Parallel encoder and decoder architecture for cyclic codes

Tomoko K. Matsushima, Toshiyasu Matsushima, Shigeichi Hirasawa

Research output: Contribution to journalArticle

18 Citations (Scopus)

Abstract

Recently, the high-speed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of high-speed error correction circuits. Parallel processing has been found to be an effective method of speeding up operations, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows // symbols to be processed in parallel, where // is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols /J. As an example, we investigate hardware complexity for a Reed-Solomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of// conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with //, the proposed architecture is more efficient than a setup using // conventional circuits for high data rate applications. It is also suggested that a parallel Reed-Solomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.

Original languageEnglish
Pages (from-to)1313-1322
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE79-A
Issue number9
Publication statusPublished - 1996
Externally publishedYes

Fingerprint

Cyclic Codes
Encoder
Networks (circuits)
Hardware
High Speed
Reed-Solomon codes
Binary codes
Parallel architectures
BCH Codes
Error correction
Reed-Solomon Codes
Light transmission
Critical Path
Parallel Architectures
Data communication systems
Binary Code
Path Length
Error Correction
Clocks
Parallel Processing

Keywords

  • Circuit design
  • Cyclic code
  • Decoder
  • Encoder
  • Error correction
  • Parallel architecture

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

Parallel encoder and decoder architecture for cyclic codes. / Matsushima, Tomoko K.; Matsushima, Toshiyasu; Hirasawa, Shigeichi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E79-A, No. 9, 1996, p. 1313-1322.

Research output: Contribution to journalArticle

@article{45d0d2abf471424f92b36e08d078cbf7,
title = "Parallel encoder and decoder architecture for cyclic codes",
abstract = "Recently, the high-speed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of high-speed error correction circuits. Parallel processing has been found to be an effective method of speeding up operations, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows // symbols to be processed in parallel, where // is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols /J. As an example, we investigate hardware complexity for a Reed-Solomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of// conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with //, the proposed architecture is more efficient than a setup using // conventional circuits for high data rate applications. It is also suggested that a parallel Reed-Solomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.",
keywords = "Circuit design, Cyclic code, Decoder, Encoder, Error correction, Parallel architecture",
author = "Matsushima, {Tomoko K.} and Toshiyasu Matsushima and Shigeichi Hirasawa",
year = "1996",
language = "English",
volume = "E79-A",
pages = "1313--1322",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "9",

}

TY - JOUR

T1 - Parallel encoder and decoder architecture for cyclic codes

AU - Matsushima, Tomoko K.

AU - Matsushima, Toshiyasu

AU - Hirasawa, Shigeichi

PY - 1996

Y1 - 1996

N2 - Recently, the high-speed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of high-speed error correction circuits. Parallel processing has been found to be an effective method of speeding up operations, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows // symbols to be processed in parallel, where // is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols /J. As an example, we investigate hardware complexity for a Reed-Solomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of// conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with //, the proposed architecture is more efficient than a setup using // conventional circuits for high data rate applications. It is also suggested that a parallel Reed-Solomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.

AB - Recently, the high-speed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of high-speed error correction circuits. Parallel processing has been found to be an effective method of speeding up operations, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows // symbols to be processed in parallel, where // is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols /J. As an example, we investigate hardware complexity for a Reed-Solomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of// conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with //, the proposed architecture is more efficient than a setup using // conventional circuits for high data rate applications. It is also suggested that a parallel Reed-Solomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.

KW - Circuit design

KW - Cyclic code

KW - Decoder

KW - Encoder

KW - Error correction

KW - Parallel architecture

UR - http://www.scopus.com/inward/record.url?scp=0030233272&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030233272&partnerID=8YFLogxK

M3 - Article

VL - E79-A

SP - 1313

EP - 1322

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 9

ER -