Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application

Yiqing Huang, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

One Super Hi-Vision (SHV) 4kx4k@60fps fractional motion estimation (FME) engine is proposed in this paper. Firstly, the mode reduction and edge detection techniques are adopted to filter out unpromising modes in the algorithm level. Secondly, two parallel improved schemes, called 16-pel scale processing and MB-split assignment, are given out in hardware level, which reduces design effort to only 217MHz. Moreover, sub-sampling technique is adopted during SATD (sum-of-absolute-transformed-difference) generation, which saves 75% hardware cost. By using TSMC O.18um in worst work conditions (1.62 V, 125° C), our FME engine can achieve SHV 4kx4k@60fps real-time processing with 547.5k gates hardware.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages183-186
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
Duration: 2009 Oct 202009 Oct 23

Publication series

NameASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
CountryChina
CityChangsha
Period09/10/2009/10/23

    Fingerprint

Keywords

  • FME
  • H.264/AVC
  • Super Hi-Vision

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Huang, Y., & Ikenaga, T. (2009). Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application. In ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC (pp. 183-186). [5351576] (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC). https://doi.org/10.1109/ASICON.2009.5351576