Parallel processing using data localization for MPEG2 encoding on OSCAR chip multiprocessor

Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    Currently, many people are enjoying multimedia applications with image and audio processing on PCs, PDAs, mobile phones and so on. With the popularization of the multimedia applications, needs for low cost, low power consumption and high performance processors has been increasing.To this end, chip multiprocessor architectures which allow us to attain scalable performance improvement by using multigrain parallelism are attracting much attention. However, in order to extract higher performance on a chip multiprocessor, more sophisticated software techniques are required, such as decomposing a program into adequate grain of tasks, assigning them onto processors considering parallelism, data locality optimization and so on. This paper describes a parallel processing scheme for MPEG2 encoding using data localization which improve execution efficiency assigning coarse grain tasks sharing same data on a same processor consecutively for a chip multiprocessor. The performance evaluation on OSCAR chip multiprocessor architecture shows that proposed scheme gives us 6.97 times speedup using 8 processors and 10.93 times speedup using 16 processors against sequential execution time respectively. Moreover, the proposed scheme gives us 1.61 times speedup using 8 processors and 2.08 times speedup using 16 processors against loop parallel processing which has been widely used for multiprocessor systems using the same number of processors.

    Original languageEnglish
    Title of host publicationProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
    EditorsA. Veidenbaum, H. Nakajo
    Pages119-127
    Number of pages9
    DOIs
    Publication statusPublished - 2004
    EventProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004 - Maui, HI
    Duration: 2004 Jan 122004 Jan 14

    Other

    OtherProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004
    CityMaui, HI
    Period04/1/1204/1/14

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    ASJC Scopus subject areas

    • Computer Science(all)

    Cite this

    Kodaka, T., Nakano, H., Kimura, K., & Kasahara, H. (2004). Parallel processing using data localization for MPEG2 encoding on OSCAR chip multiprocessor. In A. Veidenbaum, & H. Nakajo (Eds.), Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems (pp. 119-127) https://doi.org/10.1109/IWIA.2004.10021