Partially-parallel irregular LDPC decoder based on improved message passing schedule

Xing Li, Kazunori Shimizu, Zhen Qiu, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a new efficient message-passing schedule for irregular LPDC code. Our approach is based on the schedule designed for regular LDPC code in Ref.[8]. We have modified the original schedule for regular LDPC code and improved it particularly for the irregular LDPC coder realization. The experimental results show that our method could achieve better performance than conventional one, and improve the converging rate as well.

Original languageEnglish
Title of host publicationMidwest Symposium on Circuits and Systems
Pages1473-1476
Number of pages4
DOIs
Publication statusPublished - 2007
Event2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference - Montreal, QC
Duration: 2007 Aug 52007 Aug 8

Other

Other2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
CityMontreal, QC
Period07/8/507/8/8

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Message passing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Li, X., Shimizu, K., Qiu, Z., Ikenaga, T., & Goto, S. (2007). Partially-parallel irregular LDPC decoder based on improved message passing schedule. In Midwest Symposium on Circuits and Systems (pp. 1473-1476). [4488821] https://doi.org/10.1109/MWSCAS.2007.4488821

Partially-parallel irregular LDPC decoder based on improved message passing schedule. / Li, Xing; Shimizu, Kazunori; Qiu, Zhen; Ikenaga, Takeshi; Goto, Satoshi.

Midwest Symposium on Circuits and Systems. 2007. p. 1473-1476 4488821.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, X, Shimizu, K, Qiu, Z, Ikenaga, T & Goto, S 2007, Partially-parallel irregular LDPC decoder based on improved message passing schedule. in Midwest Symposium on Circuits and Systems., 4488821, pp. 1473-1476, 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference, Montreal, QC, 07/8/5. https://doi.org/10.1109/MWSCAS.2007.4488821
Li X, Shimizu K, Qiu Z, Ikenaga T, Goto S. Partially-parallel irregular LDPC decoder based on improved message passing schedule. In Midwest Symposium on Circuits and Systems. 2007. p. 1473-1476. 4488821 https://doi.org/10.1109/MWSCAS.2007.4488821
Li, Xing ; Shimizu, Kazunori ; Qiu, Zhen ; Ikenaga, Takeshi ; Goto, Satoshi. / Partially-parallel irregular LDPC decoder based on improved message passing schedule. Midwest Symposium on Circuits and Systems. 2007. pp. 1473-1476
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