Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Kazunori Shimizu; Tatsuyuki Ishikawa; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/ICCD.2005.83

Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Kazunori Shimizu^*, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

31 Citations (Scopus)

Abstract

This paper proposes a partially-parallel LDPC decoder based on a high-efficiency message-passing algorithm. Our proposed partially-parallel LDPC decoder performs the column operations for bit nodes in conjunction with the row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to perform column operations for every bit node connected to each of check nodes which are updated by the row operations in parallel. Our proposed LDPC decoder improves the timing when the column operations are performed, accordingly it improves the message-passing efficiency within the limited number of iterations for decoding. We implemented the proposed partially-parallel LDPC decoder on an FPGA, and simulated its decoding performance. Practical simulation shows that our proposed LDPC decoder reduces the number of iterations for decoding, and it improves the bit error performance with a small hardware overhead.

Original language	English
Title of host publication	Proceedings - 2005 IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors, ICCD 2005
Pages	503-510
Number of pages	8
DOIs	https://doi.org/10.1109/ICCD.2005.83
Publication status	Published - 2005 Dec 1
Event	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, United States Duration: 2005 Oct 2 → 2005 Oct 5

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume	2005
ISSN (Print)	1063-6404

Conference

Conference	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
Country/Territory	United States
City	San Jose, CA
Period	05/10/2 → 05/10/5

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2005.83

Cite this

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T., & Goto, S. (2005). Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 (pp. 503-510). [1524200] (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005). https://doi.org/10.1109/ICCD.2005.83

Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. / Shimizu, Kazunori; Ishikawa, Tatsuyuki; Togawa, Nozomu et al.

Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 503-510 1524200 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shimizu, K, Ishikawa, T, Togawa, N , Ikenaga, T & Goto, S 2005, Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. in Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005., 1524200, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, vol. 2005, pp. 503-510, 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005, San Jose, CA, United States, 05/10/2. https://doi.org/10.1109/ICCD.2005.83

Shimizu K, Ishikawa T, Togawa N , Ikenaga T, Goto S. Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 503-510. 1524200. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). doi: 10.1109/ICCD.2005.83

Shimizu, Kazunori ; Ishikawa, Tatsuyuki ; Togawa, Nozomu et al. / Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. pp. 503-510 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

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Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

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