Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Citations (Scopus)

Abstract

This paper proposes a partially-parallel LDPC decoder based on a high-efficiency message-passing algorithm. Our proposed partially-parallel LDPC decoder performs the column operations for bit nodes in conjunction with the row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to perform column operations for every bit node connected to each of check nodes which are updated by the row operations in parallel. Our proposed LDPC decoder improves the timing when the column operations are performed, accordingly it improves the message-passing efficiency within the limited number of iterations for decoding. We implemented the proposed partially-parallel LDPC decoder on an FPGA, and simulated its decoding performance. Practical simulation shows that our proposed LDPC decoder reduces the number of iterations for decoding, and it improves the bit error performance with a small hardware overhead.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Pages503-510
Number of pages8
Volume2005
DOIs
Publication statusPublished - 2005
Event2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA
Duration: 2005 Oct 22005 Oct 5

Other

Other2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
CitySan Jose, CA
Period05/10/205/10/5

Fingerprint

Message passing
Decoding
Field programmable gate arrays (FPGA)
Pipelines
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T., & Goto, S. (2005). Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (Vol. 2005, pp. 503-510). [1524200] https://doi.org/10.1109/ICCD.2005.83

Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. / Shimizu, Kazunori; Ishikawa, Tatsuyuki; Togawa, Nozomu; Ikenaga, Takeshi; Goto, Satoshi.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Vol. 2005 2005. p. 503-510 1524200.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shimizu, K, Ishikawa, T, Togawa, N, Ikenaga, T & Goto, S 2005, Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. vol. 2005, 1524200, pp. 503-510, 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005, San Jose, CA, 05/10/2. https://doi.org/10.1109/ICCD.2005.83
Shimizu K, Ishikawa T, Togawa N, Ikenaga T, Goto S. Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Vol. 2005. 2005. p. 503-510. 1524200 https://doi.org/10.1109/ICCD.2005.83
Shimizu, Kazunori ; Ishikawa, Tatsuyuki ; Togawa, Nozomu ; Ikenaga, Takeshi ; Goto, Satoshi. / Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Vol. 2005 2005. pp. 503-510
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