Partitioning-based multiplexer network synthesis for field-data extractors

Koki Ito, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    As seen in packet analysis of TCP/IP offload engine and stream data processing for video/audio data, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M, N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers. However, the number of required multiplexers increases too much as the input/output byte lengths increase. How to reduce the number of its required multiplexers is a major challenge. In this paper, we propose an efficient multiplexer network synthesis method for an (M, N)-field-data extractor. Our method is based on inserting an (N + B-1)-byte virtual intermediate register into a multiplexer network and partitioning it into an upper network and a lower network. Our method theoretically reduces the number of required multiplexers without increasing the multiplexer network depth. We also propose how to determine the size of the virtual intermediate register that minimizes the number of required multiplexers. Experimental results show that our method reduces the required number of gates to implement a field-data extractor by up to 92% compared with the one using a naive multiplexer network.

    Original languageEnglish
    Title of host publicationInternational System on Chip Conference
    PublisherIEEE Computer Society
    Pages263-268
    Number of pages6
    Volume2016-February
    ISBN (Print)9781467390934
    DOIs
    Publication statusPublished - 2016 Feb 12
    Event28th IEEE International System on Chip Conference, SOCC 2015 - Beijing, China
    Duration: 2015 Sep 82015 Sep 11

    Other

    Other28th IEEE International System on Chip Conference, SOCC 2015
    CountryChina
    CityBeijing
    Period15/9/815/9/11

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    Engines

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Control and Systems Engineering
    • Electrical and Electronic Engineering

    Cite this

    Ito, K., Tamiya, Y., Yanagisawa, M., & Togawa, N. (2016). Partitioning-based multiplexer network synthesis for field-data extractors. In International System on Chip Conference (Vol. 2016-February, pp. 263-268). [7406960] IEEE Computer Society. https://doi.org/10.1109/SOCC.2015.7406960

    Partitioning-based multiplexer network synthesis for field-data extractors. / Ito, Koki; Tamiya, Yutaka; Yanagisawa, Masao; Togawa, Nozomu.

    International System on Chip Conference. Vol. 2016-February IEEE Computer Society, 2016. p. 263-268 7406960.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Ito, K, Tamiya, Y, Yanagisawa, M & Togawa, N 2016, Partitioning-based multiplexer network synthesis for field-data extractors. in International System on Chip Conference. vol. 2016-February, 7406960, IEEE Computer Society, pp. 263-268, 28th IEEE International System on Chip Conference, SOCC 2015, Beijing, China, 15/9/8. https://doi.org/10.1109/SOCC.2015.7406960
    Ito K, Tamiya Y, Yanagisawa M, Togawa N. Partitioning-based multiplexer network synthesis for field-data extractors. In International System on Chip Conference. Vol. 2016-February. IEEE Computer Society. 2016. p. 263-268. 7406960 https://doi.org/10.1109/SOCC.2015.7406960
    Ito, Koki ; Tamiya, Yutaka ; Yanagisawa, Masao ; Togawa, Nozomu. / Partitioning-based multiplexer network synthesis for field-data extractors. International System on Chip Conference. Vol. 2016-February IEEE Computer Society, 2016. pp. 263-268
    @inproceedings{8a3a99be871c4a5091778aa8fd149dc4,
    title = "Partitioning-based multiplexer network synthesis for field-data extractors",
    abstract = "As seen in packet analysis of TCP/IP offload engine and stream data processing for video/audio data, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M, N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers. However, the number of required multiplexers increases too much as the input/output byte lengths increase. How to reduce the number of its required multiplexers is a major challenge. In this paper, we propose an efficient multiplexer network synthesis method for an (M, N)-field-data extractor. Our method is based on inserting an (N + B-1)-byte virtual intermediate register into a multiplexer network and partitioning it into an upper network and a lower network. Our method theoretically reduces the number of required multiplexers without increasing the multiplexer network depth. We also propose how to determine the size of the virtual intermediate register that minimizes the number of required multiplexers. Experimental results show that our method reduces the required number of gates to implement a field-data extractor by up to 92{\%} compared with the one using a naive multiplexer network.",
    author = "Koki Ito and Yutaka Tamiya and Masao Yanagisawa and Nozomu Togawa",
    year = "2016",
    month = "2",
    day = "12",
    doi = "10.1109/SOCC.2015.7406960",
    language = "English",
    isbn = "9781467390934",
    volume = "2016-February",
    pages = "263--268",
    booktitle = "International System on Chip Conference",
    publisher = "IEEE Computer Society",

    }

    TY - GEN

    T1 - Partitioning-based multiplexer network synthesis for field-data extractors

    AU - Ito, Koki

    AU - Tamiya, Yutaka

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2016/2/12

    Y1 - 2016/2/12

    N2 - As seen in packet analysis of TCP/IP offload engine and stream data processing for video/audio data, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M, N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers. However, the number of required multiplexers increases too much as the input/output byte lengths increase. How to reduce the number of its required multiplexers is a major challenge. In this paper, we propose an efficient multiplexer network synthesis method for an (M, N)-field-data extractor. Our method is based on inserting an (N + B-1)-byte virtual intermediate register into a multiplexer network and partitioning it into an upper network and a lower network. Our method theoretically reduces the number of required multiplexers without increasing the multiplexer network depth. We also propose how to determine the size of the virtual intermediate register that minimizes the number of required multiplexers. Experimental results show that our method reduces the required number of gates to implement a field-data extractor by up to 92% compared with the one using a naive multiplexer network.

    AB - As seen in packet analysis of TCP/IP offload engine and stream data processing for video/audio data, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M, N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers. However, the number of required multiplexers increases too much as the input/output byte lengths increase. How to reduce the number of its required multiplexers is a major challenge. In this paper, we propose an efficient multiplexer network synthesis method for an (M, N)-field-data extractor. Our method is based on inserting an (N + B-1)-byte virtual intermediate register into a multiplexer network and partitioning it into an upper network and a lower network. Our method theoretically reduces the number of required multiplexers without increasing the multiplexer network depth. We also propose how to determine the size of the virtual intermediate register that minimizes the number of required multiplexers. Experimental results show that our method reduces the required number of gates to implement a field-data extractor by up to 92% compared with the one using a naive multiplexer network.

    UR - http://www.scopus.com/inward/record.url?scp=84962359369&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84962359369&partnerID=8YFLogxK

    U2 - 10.1109/SOCC.2015.7406960

    DO - 10.1109/SOCC.2015.7406960

    M3 - Conference contribution

    SN - 9781467390934

    VL - 2016-February

    SP - 263

    EP - 268

    BT - International System on Chip Conference

    PB - IEEE Computer Society

    ER -