Abstract
In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.
| Original language | English |
|---|---|
| Title of host publication | ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems |
| Pages | 921-924 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris Duration: 2010 May 30 → 2010 Jun 2 |
Other
| Other | 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 |
|---|---|
| City | Paris |
| Period | 10/5/30 → 10/6/2 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. / Ohchi, Akira; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 921-924 5537401.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation
AU - Ohchi, Akira
AU - Togawa, Nozomu
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2010
Y1 - 2010
N2 - In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.
AB - In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.
UR - http://www.scopus.com/inward/record.url?scp=77955998595&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955998595&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2010.5537401
DO - 10.1109/ISCAS.2010.5537401
M3 - Conference contribution
SN - 9781424453085
SP - 921
EP - 924
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
ER -