Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.

    Original languageEnglish
    Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
    Pages921-924
    Number of pages4
    DOIs
    Publication statusPublished - 2010
    Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris
    Duration: 2010 May 302010 Jun 2

    Other

    Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
    CityParis
    Period10/5/3010/6/2

    Fingerprint

    Controllers
    Scheduling
    High level synthesis

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Ohchi, A., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2010). Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 921-924). [5537401] https://doi.org/10.1109/ISCAS.2010.5537401

    Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. / Ohchi, Akira; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 921-924 5537401.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Ohchi, A, Togawa, N, Yanagisawa, M & Ohtsuki, T 2010, Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537401, pp. 921-924, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537401
    Ohchi A, Togawa N, Yanagisawa M, Ohtsuki T. Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 921-924. 5537401 https://doi.org/10.1109/ISCAS.2010.5537401
    Ohchi, Akira ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 921-924
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