Performance evaluation of compiler controlled power saving scheme

Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    Multicore processors, or chip multiprocessors, which allow us to realize low power consumption, high effective performance, good cost performance and short hardware/software development period, are attracting much attention. In order to achieve full potential of multicore processors, cooperation with a parallelizing compiler is very important. The latest compiler extracts multilevel parallelism, such as coarse grain task parallelism, loop parallelism and near fine grain parallelism, to keep parallel execution efficiency high. It also controls voltage and clock frequency of processors carefully to reduce energy consumption during execution of an application program. This paper evaluates performance of compiler controlled power saving scheme which has been implemented in OSCAR multigrain parallelizing compiler. The developed power saving scheme realizes voltage/frequency control and power shutdown of each processor core during coarse grain task parallel processing. In performance evaluation, when static power is assumed as one-tenth of dynamic power, OSCAR compiler with the power saving scheme achieved 61.2 percent energy reduction for SPEC CFP95 applu without performance degradation on 4 processors and 87.4 percent energy reduction for mpeg2encode, 88.1 percent energy reduction for SPEC CFP95 tomcatv and 84.6 percent energy reduction for applu with real-time deadline constraint on 4 processors.

    Original languageEnglish
    Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    Pages480-493
    Number of pages14
    Volume4759 LNCS
    Publication statusPublished - 2008
    Event6th International Symposium on High Performance Computing, ISHPC 2005 and 1st International Workshop on Advanced Low Power Systems, ALPS 2006 - 6th International Symposium on High
    Duration: 2005 Sep 72005 Sep 9

    Publication series

    NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    Volume4759 LNCS
    ISSN (Print)03029743
    ISSN (Electronic)16113349

    Other

    Other6th International Symposium on High Performance Computing, ISHPC 2005 and 1st International Workshop on Advanced Low Power Systems, ALPS 2006
    City6th International Symposium on High
    Period05/9/705/9/9

    Fingerprint

    Power Saving
    Compiler
    Percent
    Parallelism
    Performance Evaluation
    Software
    Parallelizing Compilers
    Costs and Cost Analysis
    Multi-core Processor
    Energy
    Voltage
    Chip multiprocessors
    Plant shutdowns
    Deadline
    Parallel Processing
    Application programs
    Voltage control
    Software Development
    Computer hardware
    Power Consumption

    ASJC Scopus subject areas

    • Computer Science(all)
    • Biochemistry, Genetics and Molecular Biology(all)
    • Theoretical Computer Science

    Cite this

    Shirako, J., Yoshida, M., Oshiyama, N., Wada, Y., Nakano, H., Shikano, H., ... Kasahara, H. (2008). Performance evaluation of compiler controlled power saving scheme. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4759 LNCS, pp. 480-493). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4759 LNCS).

    Performance evaluation of compiler controlled power saving scheme. / Shirako, Jun; Yoshida, Munehiro; Oshiyama, Naoto; Wada, Yasutaka; Nakano, Hirofumi; Shikano, Hiroaki; Kimura, Keiji; Kasahara, Hironori.

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4759 LNCS 2008. p. 480-493 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4759 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Shirako, J, Yoshida, M, Oshiyama, N, Wada, Y, Nakano, H, Shikano, H, Kimura, K & Kasahara, H 2008, Performance evaluation of compiler controlled power saving scheme. in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). vol. 4759 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4759 LNCS, pp. 480-493, 6th International Symposium on High Performance Computing, ISHPC 2005 and 1st International Workshop on Advanced Low Power Systems, ALPS 2006, 6th International Symposium on High, 05/9/7.
    Shirako J, Yoshida M, Oshiyama N, Wada Y, Nakano H, Shikano H et al. Performance evaluation of compiler controlled power saving scheme. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4759 LNCS. 2008. p. 480-493. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
    Shirako, Jun ; Yoshida, Munehiro ; Oshiyama, Naoto ; Wada, Yasutaka ; Nakano, Hirofumi ; Shikano, Hiroaki ; Kimura, Keiji ; Kasahara, Hironori. / Performance evaluation of compiler controlled power saving scheme. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4759 LNCS 2008. pp. 480-493 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
    @inproceedings{29026e5a624a4d818de1e1e49f2fafdb,
    title = "Performance evaluation of compiler controlled power saving scheme",
    abstract = "Multicore processors, or chip multiprocessors, which allow us to realize low power consumption, high effective performance, good cost performance and short hardware/software development period, are attracting much attention. In order to achieve full potential of multicore processors, cooperation with a parallelizing compiler is very important. The latest compiler extracts multilevel parallelism, such as coarse grain task parallelism, loop parallelism and near fine grain parallelism, to keep parallel execution efficiency high. It also controls voltage and clock frequency of processors carefully to reduce energy consumption during execution of an application program. This paper evaluates performance of compiler controlled power saving scheme which has been implemented in OSCAR multigrain parallelizing compiler. The developed power saving scheme realizes voltage/frequency control and power shutdown of each processor core during coarse grain task parallel processing. In performance evaluation, when static power is assumed as one-tenth of dynamic power, OSCAR compiler with the power saving scheme achieved 61.2 percent energy reduction for SPEC CFP95 applu without performance degradation on 4 processors and 87.4 percent energy reduction for mpeg2encode, 88.1 percent energy reduction for SPEC CFP95 tomcatv and 84.6 percent energy reduction for applu with real-time deadline constraint on 4 processors.",
    author = "Jun Shirako and Munehiro Yoshida and Naoto Oshiyama and Yasutaka Wada and Hirofumi Nakano and Hiroaki Shikano and Keiji Kimura and Hironori Kasahara",
    year = "2008",
    language = "English",
    isbn = "3540777032",
    volume = "4759 LNCS",
    series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
    pages = "480--493",
    booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

    }

    TY - GEN

    T1 - Performance evaluation of compiler controlled power saving scheme

    AU - Shirako, Jun

    AU - Yoshida, Munehiro

    AU - Oshiyama, Naoto

    AU - Wada, Yasutaka

    AU - Nakano, Hirofumi

    AU - Shikano, Hiroaki

    AU - Kimura, Keiji

    AU - Kasahara, Hironori

    PY - 2008

    Y1 - 2008

    N2 - Multicore processors, or chip multiprocessors, which allow us to realize low power consumption, high effective performance, good cost performance and short hardware/software development period, are attracting much attention. In order to achieve full potential of multicore processors, cooperation with a parallelizing compiler is very important. The latest compiler extracts multilevel parallelism, such as coarse grain task parallelism, loop parallelism and near fine grain parallelism, to keep parallel execution efficiency high. It also controls voltage and clock frequency of processors carefully to reduce energy consumption during execution of an application program. This paper evaluates performance of compiler controlled power saving scheme which has been implemented in OSCAR multigrain parallelizing compiler. The developed power saving scheme realizes voltage/frequency control and power shutdown of each processor core during coarse grain task parallel processing. In performance evaluation, when static power is assumed as one-tenth of dynamic power, OSCAR compiler with the power saving scheme achieved 61.2 percent energy reduction for SPEC CFP95 applu without performance degradation on 4 processors and 87.4 percent energy reduction for mpeg2encode, 88.1 percent energy reduction for SPEC CFP95 tomcatv and 84.6 percent energy reduction for applu with real-time deadline constraint on 4 processors.

    AB - Multicore processors, or chip multiprocessors, which allow us to realize low power consumption, high effective performance, good cost performance and short hardware/software development period, are attracting much attention. In order to achieve full potential of multicore processors, cooperation with a parallelizing compiler is very important. The latest compiler extracts multilevel parallelism, such as coarse grain task parallelism, loop parallelism and near fine grain parallelism, to keep parallel execution efficiency high. It also controls voltage and clock frequency of processors carefully to reduce energy consumption during execution of an application program. This paper evaluates performance of compiler controlled power saving scheme which has been implemented in OSCAR multigrain parallelizing compiler. The developed power saving scheme realizes voltage/frequency control and power shutdown of each processor core during coarse grain task parallel processing. In performance evaluation, when static power is assumed as one-tenth of dynamic power, OSCAR compiler with the power saving scheme achieved 61.2 percent energy reduction for SPEC CFP95 applu without performance degradation on 4 processors and 87.4 percent energy reduction for mpeg2encode, 88.1 percent energy reduction for SPEC CFP95 tomcatv and 84.6 percent energy reduction for applu with real-time deadline constraint on 4 processors.

    UR - http://www.scopus.com/inward/record.url?scp=38549108530&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=38549108530&partnerID=8YFLogxK

    M3 - Conference contribution

    AN - SCOPUS:38549108530

    SN - 3540777032

    SN - 9783540777038

    VL - 4759 LNCS

    T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

    SP - 480

    EP - 493

    BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

    ER -