### Abstract

This paper proposes a circuit partitioning algorithm in which the delay of each critical signal path is within a specified upper bound. Its core is recursive bipartitioning of a circuit which consists of three stages: 0) detection of critical paths; 1) bipartitioning of a set of primary inputs and outputs; and 2) bipartitioning of a set of logic-blocks. In 0), the algorithm detects the critical paths based on their lower bounds of delays. The delays of the critical paths are reduced with higher priority. In 1), the algorithm attempts to assign the primary input and output on each critical path to one chip. In 2), the algorithm not only decreases the number of crossings between chips but also assigns the logic-blocks on each critical path to one chip by exploiting a network flow technique with logic-block replication. The experimental results demonstrate that it resolves almost all path delay constraints with maintaining the maximum number of required I/O blocks per chip small compared with conventional algorithms.

Original language | English |
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Title of host publication | IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings |

Place of Publication | Piscataway, NJ, United States |

Publisher | IEEE |

Pages | 294-297 |

Number of pages | 4 |

Publication status | Published - 1996 |

Event | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea Duration: 1996 Nov 18 → 1996 Nov 21 |

### Other

Other | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems |
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City | Seoul, South Korea |

Period | 96/11/18 → 96/11/21 |

### Fingerprint

### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### Cite this

*IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings*(pp. 294-297). Piscataway, NJ, United States: IEEE.

**Performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems.** / Togawa, Nozomu; Sato, Masao; Ohtsuki, Tatsuo.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings.*IEEE, Piscataway, NJ, United States, pp. 294-297, Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems, Seoul, South Korea, 96/11/18.

}

TY - GEN

T1 - Performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

AU - Togawa, Nozomu

AU - Sato, Masao

AU - Ohtsuki, Tatsuo

PY - 1996

Y1 - 1996

N2 - This paper proposes a circuit partitioning algorithm in which the delay of each critical signal path is within a specified upper bound. Its core is recursive bipartitioning of a circuit which consists of three stages: 0) detection of critical paths; 1) bipartitioning of a set of primary inputs and outputs; and 2) bipartitioning of a set of logic-blocks. In 0), the algorithm detects the critical paths based on their lower bounds of delays. The delays of the critical paths are reduced with higher priority. In 1), the algorithm attempts to assign the primary input and output on each critical path to one chip. In 2), the algorithm not only decreases the number of crossings between chips but also assigns the logic-blocks on each critical path to one chip by exploiting a network flow technique with logic-block replication. The experimental results demonstrate that it resolves almost all path delay constraints with maintaining the maximum number of required I/O blocks per chip small compared with conventional algorithms.

AB - This paper proposes a circuit partitioning algorithm in which the delay of each critical signal path is within a specified upper bound. Its core is recursive bipartitioning of a circuit which consists of three stages: 0) detection of critical paths; 1) bipartitioning of a set of primary inputs and outputs; and 2) bipartitioning of a set of logic-blocks. In 0), the algorithm detects the critical paths based on their lower bounds of delays. The delays of the critical paths are reduced with higher priority. In 1), the algorithm attempts to assign the primary input and output on each critical path to one chip. In 2), the algorithm not only decreases the number of crossings between chips but also assigns the logic-blocks on each critical path to one chip by exploiting a network flow technique with logic-block replication. The experimental results demonstrate that it resolves almost all path delay constraints with maintaining the maximum number of required I/O blocks per chip small compared with conventional algorithms.

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UR - http://www.scopus.com/inward/citedby.url?scp=0030403082&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0030403082

SP - 294

EP - 297

BT - IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

PB - IEEE

CY - Piscataway, NJ, United States

ER -