Performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    This paper proposes a circuit partitioning algorithm in which the delay of each critical signal path is within a specified upper bound. Its core is recursive bipartitioning of a circuit which consists of three stages: 0) detection of critical paths; 1) bipartitioning of a set of primary inputs and outputs; and 2) bipartitioning of a set of logic-blocks. In 0), the algorithm detects the critical paths based on their lower bounds of delays. The delays of the critical paths are reduced with higher priority. In 1), the algorithm attempts to assign the primary input and output on each critical path to one chip. In 2), the algorithm not only decreases the number of crossings between chips but also assigns the logic-blocks on each critical path to one chip by exploiting a network flow technique with logic-block replication. The experimental results demonstrate that it resolves almost all path delay constraints with maintaining the maximum number of required I/O blocks per chip small compared with conventional algorithms.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
    Place of PublicationPiscataway, NJ, United States
    PublisherIEEE
    Pages294-297
    Number of pages4
    Publication statusPublished - 1996
    EventProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea
    Duration: 1996 Nov 181996 Nov 21

    Other

    OtherProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems
    CitySeoul, South Korea
    Period96/11/1896/11/21

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    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Togawa, N., Sato, M., & Ohtsuki, T. (1996). Performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems. In IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings (pp. 294-297). IEEE.