Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling

Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS with error detection. The proposed circuit, Phase-Adjustable Error Detection Flip-Flip (PEDFF), adjusts the clock phase of an additional FF for the timing error detection, based on the timing slack. 2-Stage Hold-Driven Optimization (2-SHDO) technology splits the hold-driven optimization in two stages. Slack-Based Grouping Scheme (SBGS) technology divides each timing path into appropriate groups based on the timing slack. Slack Distribution Control (SDC) technology improves the sharp distribution of the path delay at which the logic synthesis tool has relaxed the delay. We evaluate the methodology by simulating a 32-bit microprocessor in 90 nm CMOS technology. The proposed methodology reduces the energy consumption by 19.8% compared to non-DVS. The OR-tree's latency is shortened to 16.3% compared to the conventional DVS. The area and power penalties for delay buffers on short paths are reduced to 35.0% and 40.6% compared to the conventional DVS, respectively. The proposed methodology with SDC reduces the energy consumption by 17.0% on another example with the sharp slack distribution by the logic synthesis compared to non-DVS.

Original languageEnglish
Article number17
JournalACM Transactions on Design Automation of Electronic Systems
Volume15
Issue number2
DOIs
Publication statusPublished - 2010 Feb 1
Externally publishedYes

Fingerprint

Flip flop circuits
Error detection
Energy utilization
Networks (circuits)
Voltage scaling
Microprocessor chips
Clocks

Keywords

  • CTS
  • DVS
  • Error detection flip-flop
  • P & R
  • STA

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling. / Kurimoto, Masanori; Suzuki, Hiroaki; Akiyama, Rei; Yamanaka, Tadao; Ohkuma, Haruyuki; Takata, Hidehiro; Shinohara, Hirofumi.

In: ACM Transactions on Design Automation of Electronic Systems, Vol. 15, No. 2, 17, 01.02.2010.

Research output: Contribution to journalArticle

@article{b247d97604ce4cae842b4b8eedb33b89,
title = "Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling",
abstract = "For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS with error detection. The proposed circuit, Phase-Adjustable Error Detection Flip-Flip (PEDFF), adjusts the clock phase of an additional FF for the timing error detection, based on the timing slack. 2-Stage Hold-Driven Optimization (2-SHDO) technology splits the hold-driven optimization in two stages. Slack-Based Grouping Scheme (SBGS) technology divides each timing path into appropriate groups based on the timing slack. Slack Distribution Control (SDC) technology improves the sharp distribution of the path delay at which the logic synthesis tool has relaxed the delay. We evaluate the methodology by simulating a 32-bit microprocessor in 90 nm CMOS technology. The proposed methodology reduces the energy consumption by 19.8{\%} compared to non-DVS. The OR-tree's latency is shortened to 16.3{\%} compared to the conventional DVS. The area and power penalties for delay buffers on short paths are reduced to 35.0{\%} and 40.6{\%} compared to the conventional DVS, respectively. The proposed methodology with SDC reduces the energy consumption by 17.0{\%} on another example with the sharp slack distribution by the logic synthesis compared to non-DVS.",
keywords = "CTS, DVS, Error detection flip-flop, P & R, STA",
author = "Masanori Kurimoto and Hiroaki Suzuki and Rei Akiyama and Tadao Yamanaka and Haruyuki Ohkuma and Hidehiro Takata and Hirofumi Shinohara",
year = "2010",
month = "2",
day = "1",
doi = "10.1145/1698759.1698767",
language = "English",
volume = "15",
journal = "ACM Transactions on Design Automation of Electronic Systems",
issn = "1084-4309",
publisher = "Association for Computing Machinery (ACM)",
number = "2",

}

TY - JOUR

T1 - Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling

AU - Kurimoto, Masanori

AU - Suzuki, Hiroaki

AU - Akiyama, Rei

AU - Yamanaka, Tadao

AU - Ohkuma, Haruyuki

AU - Takata, Hidehiro

AU - Shinohara, Hirofumi

PY - 2010/2/1

Y1 - 2010/2/1

N2 - For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS with error detection. The proposed circuit, Phase-Adjustable Error Detection Flip-Flip (PEDFF), adjusts the clock phase of an additional FF for the timing error detection, based on the timing slack. 2-Stage Hold-Driven Optimization (2-SHDO) technology splits the hold-driven optimization in two stages. Slack-Based Grouping Scheme (SBGS) technology divides each timing path into appropriate groups based on the timing slack. Slack Distribution Control (SDC) technology improves the sharp distribution of the path delay at which the logic synthesis tool has relaxed the delay. We evaluate the methodology by simulating a 32-bit microprocessor in 90 nm CMOS technology. The proposed methodology reduces the energy consumption by 19.8% compared to non-DVS. The OR-tree's latency is shortened to 16.3% compared to the conventional DVS. The area and power penalties for delay buffers on short paths are reduced to 35.0% and 40.6% compared to the conventional DVS, respectively. The proposed methodology with SDC reduces the energy consumption by 17.0% on another example with the sharp slack distribution by the logic synthesis compared to non-DVS.

AB - For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS with error detection. The proposed circuit, Phase-Adjustable Error Detection Flip-Flip (PEDFF), adjusts the clock phase of an additional FF for the timing error detection, based on the timing slack. 2-Stage Hold-Driven Optimization (2-SHDO) technology splits the hold-driven optimization in two stages. Slack-Based Grouping Scheme (SBGS) technology divides each timing path into appropriate groups based on the timing slack. Slack Distribution Control (SDC) technology improves the sharp distribution of the path delay at which the logic synthesis tool has relaxed the delay. We evaluate the methodology by simulating a 32-bit microprocessor in 90 nm CMOS technology. The proposed methodology reduces the energy consumption by 19.8% compared to non-DVS. The OR-tree's latency is shortened to 16.3% compared to the conventional DVS. The area and power penalties for delay buffers on short paths are reduced to 35.0% and 40.6% compared to the conventional DVS, respectively. The proposed methodology with SDC reduces the energy consumption by 17.0% on another example with the sharp slack distribution by the logic synthesis compared to non-DVS.

KW - CTS

KW - DVS

KW - Error detection flip-flop

KW - P & R

KW - STA

UR - http://www.scopus.com/inward/record.url?scp=77749243047&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77749243047&partnerID=8YFLogxK

U2 - 10.1145/1698759.1698767

DO - 10.1145/1698759.1698767

M3 - Article

AN - SCOPUS:77749243047

VL - 15

JO - ACM Transactions on Design Automation of Electronic Systems

JF - ACM Transactions on Design Automation of Electronic Systems

SN - 1084-4309

IS - 2

M1 - 17

ER -