Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling

Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
Pages884-889
Number of pages6
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event45th Design Automation Conference, DAC - Anaheim, CA, United States
Duration: 2008 Jun 82008 Jun 13

Other

Other45th Design Automation Conference, DAC
CountryUnited States
CityAnaheim, CA
Period08/6/808/6/13

    Fingerprint

Keywords

  • CTS
  • DVS
  • Error-Detection flip-flop
  • STA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Kurimoto, M., Suzuki, H., Akiyama, R., Yamanaka, T., Ohkuma, H., Takata, H., & Shinohara, H. (2008). Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling. In Proceedings - Design Automation Conference (pp. 884-889). [4555944] https://doi.org/10.1109/DAC.2008.4555944