Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization: Theory, experiments, and thin-film transistor applications

Noriyoshi Yamauchi, Rafael Reif

Research output: Contribution to journalArticle

137 Citations (Scopus)

Abstract

A review is presented of the self-implantation method which has been developed to achieve high-quality polycrystalline silicon thin films on insulators with enhanced grain sizes and its applications to thin-film transistors (TFTs). In this method, silicon ions are implanted into an as-deposited polycrystalline silicon thin film to amorphize most of the film structure. Depending on ion implantation conditions, some seeds with 〈110〉 orientation remain in the film structure due to channeling. The film is then thermally annealed at relatively low temperatures, typically in the range of 550-700°C. With optimized process conditions, average grain sizes of 1 μm or greater can be obtained. First, an overview is given of the thin-film transistor technology which has been the greatest motivation for the research and development of the self-implantation method. Then the mechanism of selective amorphization by the silicon self-implantation and the crystallization by thermal annealing is discussed. An analytical model and experimental results are described. Polycrystalline silicon TFTs fabricated using the self-implanted polycrystalline silicon thin-films are then reviewed. The high-quality polycrystalline silicon thin films processed with the self-implantation method results in excellent TFT characteristics for both n- and p-channel devices thereby allowing complementary metal-oxide-semiconductor integrated circuits. High mobilities of around 150 cm2/V s for n-channel TFTs and around 50 cm2/V s for p-channel TFTs as well as on-to-off current ratios of 1×108 have been achieved. Fabrication and characterization of polycrystalline silicon TFTs with channel dimensions comparable to or smaller than the grain size of polycrystalline silicon films are also described to present a case study to discuss the self-implantation process and associated technologies. Finally, new approaches that extend the self-implantation method to control grain-boundary locations are discussed. If grain-boundary locations can indeed be controlled, the self-implantation method will become even more valuable in developing future high-performance TFT integrated circuits.

Original languageEnglish
Pages (from-to)3235-3257
Number of pages23
JournalJournal of Applied Physics
Volume75
Issue number7
DOIs
Publication statusPublished - 1994
Externally publishedYes

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ion implantation
solid phases
transistors
crystallization
silicon
thin films
implantation
grain size
integrated circuits
grain boundaries
transistor circuits
research and development
silicon films
seeds
CMOS
insulators
fabrication
annealing

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

Cite this

@article{3464c7c3ff5949469addcd9fafc6f7c9,
title = "Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization: Theory, experiments, and thin-film transistor applications",
abstract = "A review is presented of the self-implantation method which has been developed to achieve high-quality polycrystalline silicon thin films on insulators with enhanced grain sizes and its applications to thin-film transistors (TFTs). In this method, silicon ions are implanted into an as-deposited polycrystalline silicon thin film to amorphize most of the film structure. Depending on ion implantation conditions, some seeds with 〈110〉 orientation remain in the film structure due to channeling. The film is then thermally annealed at relatively low temperatures, typically in the range of 550-700°C. With optimized process conditions, average grain sizes of 1 μm or greater can be obtained. First, an overview is given of the thin-film transistor technology which has been the greatest motivation for the research and development of the self-implantation method. Then the mechanism of selective amorphization by the silicon self-implantation and the crystallization by thermal annealing is discussed. An analytical model and experimental results are described. Polycrystalline silicon TFTs fabricated using the self-implanted polycrystalline silicon thin-films are then reviewed. The high-quality polycrystalline silicon thin films processed with the self-implantation method results in excellent TFT characteristics for both n- and p-channel devices thereby allowing complementary metal-oxide-semiconductor integrated circuits. High mobilities of around 150 cm2/V s for n-channel TFTs and around 50 cm2/V s for p-channel TFTs as well as on-to-off current ratios of 1×108 have been achieved. Fabrication and characterization of polycrystalline silicon TFTs with channel dimensions comparable to or smaller than the grain size of polycrystalline silicon films are also described to present a case study to discuss the self-implantation process and associated technologies. Finally, new approaches that extend the self-implantation method to control grain-boundary locations are discussed. If grain-boundary locations can indeed be controlled, the self-implantation method will become even more valuable in developing future high-performance TFT integrated circuits.",
author = "Noriyoshi Yamauchi and Rafael Reif",
year = "1994",
doi = "10.1063/1.356131",
language = "English",
volume = "75",
pages = "3235--3257",
journal = "Journal of Applied Physics",
issn = "0021-8979",
publisher = "American Institute of Physics Publising LLC",
number = "7",

}

TY - JOUR

T1 - Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization

T2 - Theory, experiments, and thin-film transistor applications

AU - Yamauchi, Noriyoshi

AU - Reif, Rafael

PY - 1994

Y1 - 1994

N2 - A review is presented of the self-implantation method which has been developed to achieve high-quality polycrystalline silicon thin films on insulators with enhanced grain sizes and its applications to thin-film transistors (TFTs). In this method, silicon ions are implanted into an as-deposited polycrystalline silicon thin film to amorphize most of the film structure. Depending on ion implantation conditions, some seeds with 〈110〉 orientation remain in the film structure due to channeling. The film is then thermally annealed at relatively low temperatures, typically in the range of 550-700°C. With optimized process conditions, average grain sizes of 1 μm or greater can be obtained. First, an overview is given of the thin-film transistor technology which has been the greatest motivation for the research and development of the self-implantation method. Then the mechanism of selective amorphization by the silicon self-implantation and the crystallization by thermal annealing is discussed. An analytical model and experimental results are described. Polycrystalline silicon TFTs fabricated using the self-implanted polycrystalline silicon thin-films are then reviewed. The high-quality polycrystalline silicon thin films processed with the self-implantation method results in excellent TFT characteristics for both n- and p-channel devices thereby allowing complementary metal-oxide-semiconductor integrated circuits. High mobilities of around 150 cm2/V s for n-channel TFTs and around 50 cm2/V s for p-channel TFTs as well as on-to-off current ratios of 1×108 have been achieved. Fabrication and characterization of polycrystalline silicon TFTs with channel dimensions comparable to or smaller than the grain size of polycrystalline silicon films are also described to present a case study to discuss the self-implantation process and associated technologies. Finally, new approaches that extend the self-implantation method to control grain-boundary locations are discussed. If grain-boundary locations can indeed be controlled, the self-implantation method will become even more valuable in developing future high-performance TFT integrated circuits.

AB - A review is presented of the self-implantation method which has been developed to achieve high-quality polycrystalline silicon thin films on insulators with enhanced grain sizes and its applications to thin-film transistors (TFTs). In this method, silicon ions are implanted into an as-deposited polycrystalline silicon thin film to amorphize most of the film structure. Depending on ion implantation conditions, some seeds with 〈110〉 orientation remain in the film structure due to channeling. The film is then thermally annealed at relatively low temperatures, typically in the range of 550-700°C. With optimized process conditions, average grain sizes of 1 μm or greater can be obtained. First, an overview is given of the thin-film transistor technology which has been the greatest motivation for the research and development of the self-implantation method. Then the mechanism of selective amorphization by the silicon self-implantation and the crystallization by thermal annealing is discussed. An analytical model and experimental results are described. Polycrystalline silicon TFTs fabricated using the self-implanted polycrystalline silicon thin-films are then reviewed. The high-quality polycrystalline silicon thin films processed with the self-implantation method results in excellent TFT characteristics for both n- and p-channel devices thereby allowing complementary metal-oxide-semiconductor integrated circuits. High mobilities of around 150 cm2/V s for n-channel TFTs and around 50 cm2/V s for p-channel TFTs as well as on-to-off current ratios of 1×108 have been achieved. Fabrication and characterization of polycrystalline silicon TFTs with channel dimensions comparable to or smaller than the grain size of polycrystalline silicon films are also described to present a case study to discuss the self-implantation process and associated technologies. Finally, new approaches that extend the self-implantation method to control grain-boundary locations are discussed. If grain-boundary locations can indeed be controlled, the self-implantation method will become even more valuable in developing future high-performance TFT integrated circuits.

UR - http://www.scopus.com/inward/record.url?scp=0344683554&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0344683554&partnerID=8YFLogxK

U2 - 10.1063/1.356131

DO - 10.1063/1.356131

M3 - Article

AN - SCOPUS:0344683554

VL - 75

SP - 3235

EP - 3257

JO - Journal of Applied Physics

JF - Journal of Applied Physics

SN - 0021-8979

IS - 7

ER -