Port assignment for interconnect reduction in high-level synthesis

Hao Cong, Song Chen, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper focuses on the Port Assignment Problem for Binary Commutative Operators (PAP-BCO) in high-level synthesis. Given a binding of operations and variables, the PAP-BCO pursues to build the connections of registers to functional units with an objective of minimizing the number of interconnections. In this paper, we formulate the PAP-BCO as a vertex partitioning problem on a graph, and propose an exact Integer Linear Programming (ILP) based method and a fast iterative method based on elementary transformations of spanning tree to solve it. Experimental results show that the fast iterative algorithm can get the optimum solutions in 97% runs. At the same time, the running time is only tens of milliseconds for the maximum test case with 64 registers and 140 operations, on which the ILP based method ran out of time.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
Publication statusPublished - 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu
Duration: 2012 Apr 232012 Apr 25

Other

Other2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CityHsinchu
Period12/4/2312/4/25

Fingerprint

Linear programming
Iterative methods
High level synthesis

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Cong, H., Chen, S., & Yoshimura, T. (2012). Port assignment for interconnect reduction in high-level synthesis. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212613] https://doi.org/10.1109/VLSI-DAT.2012.6212613

Port assignment for interconnect reduction in high-level synthesis. / Cong, Hao; Chen, Song; Yoshimura, Takeshi.

2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212613.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cong, H, Chen, S & Yoshimura, T 2012, Port assignment for interconnect reduction in high-level synthesis. in 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212613, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, 12/4/23. https://doi.org/10.1109/VLSI-DAT.2012.6212613
Cong H, Chen S, Yoshimura T. Port assignment for interconnect reduction in high-level synthesis. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212613 https://doi.org/10.1109/VLSI-DAT.2012.6212613
Cong, Hao ; Chen, Song ; Yoshimura, Takeshi. / Port assignment for interconnect reduction in high-level synthesis. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012.
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