Port assignment for multiplexer and interconnection optimization

Cong Hao, Hao Ran Zhang, Song Chen, Takeshi Yoshimura, Min You Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Data path connection elements usually consume a significant amount of both power and area on a VLSI chip. In this paper, we focus on the port assignment problem for multiplexer (MUX) and interconnection optimization in High-Level Synthesis. Given a binding solution of operations and variables, the port assignment problem connects the registers to the operator ports through MUXes, to minimize the interconnections between MUXes and operator ports, as well as the MUX power and area. We formulate the port assignment problem for binary commutative operators as a vertex partition problem on a graph, and propose a local search based heuristic algorithm that iteratively performs the elementary spanning tree transformation on the graph to solve it. We also propose a method to estimate the result of the tree transformation and filter a considerable amount of bad solutions in advance which greatly accelerate the algorithm. The experimental results show that our proposed algorithm is able to achieve 48% execution time reduction and 8.3% power reduction compared with the previous work, and the power reduction can be obtained for 37% test benches.

Original languageEnglish
Title of host publicationProceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013
PublisherIEEE Computer Society
Pages136-143
Number of pages8
ISBN (Print)9781479913145
DOIs
Publication statusPublished - 2013
Event5th Asia Symposium on Quality Electronic Design, ASQED 2013 - Penang
Duration: 2013 Aug 262013 Aug 28

Other

Other5th Asia Symposium on Quality Electronic Design, ASQED 2013
CityPenang
Period13/8/2613/8/28

Fingerprint

Heuristic algorithms
High level synthesis

Keywords

  • High-Level Synthesis
  • Interconnection
  • Multiplexer

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Hao, C., Zhang, H. R., Chen, S., Yoshimura, T., & Wu, M. Y. (2013). Port assignment for multiplexer and interconnection optimization. In Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013 (pp. 136-143). [6643576] IEEE Computer Society. https://doi.org/10.1109/ASQED.2013.6643576

Port assignment for multiplexer and interconnection optimization. / Hao, Cong; Zhang, Hao Ran; Chen, Song; Yoshimura, Takeshi; Wu, Min You.

Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013. IEEE Computer Society, 2013. p. 136-143 6643576.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hao, C, Zhang, HR, Chen, S, Yoshimura, T & Wu, MY 2013, Port assignment for multiplexer and interconnection optimization. in Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013., 6643576, IEEE Computer Society, pp. 136-143, 5th Asia Symposium on Quality Electronic Design, ASQED 2013, Penang, 13/8/26. https://doi.org/10.1109/ASQED.2013.6643576
Hao C, Zhang HR, Chen S, Yoshimura T, Wu MY. Port assignment for multiplexer and interconnection optimization. In Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013. IEEE Computer Society. 2013. p. 136-143. 6643576 https://doi.org/10.1109/ASQED.2013.6643576
Hao, Cong ; Zhang, Hao Ran ; Chen, Song ; Yoshimura, Takeshi ; Wu, Min You. / Port assignment for multiplexer and interconnection optimization. Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013. IEEE Computer Society, 2013. pp. 136-143
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