Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology

Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.

Original languageEnglish
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages15-20
Number of pages6
DOIs
Publication statusPublished - 2008
Externally publishedYes
EventISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design - Bangalore, India
Duration: 2008 Aug 112008 Aug 13

Other

OtherISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
CountryIndia
CityBangalore
Period08/8/1108/8/13

Fingerprint

Silicon
Specifications
Leakage currents
Fabrication
Networks (circuits)
Testing

Keywords

  • Body-Biasing
  • Device variability suppression
  • Leakage current reduction
  • Post-Silicon Programming

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Suzuki, H., Kurimoto, M., Yamanaka, T., Takata, H., Makino, H., & Shinohara, H. (2008). Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 15-20) https://doi.org/10.1145/1393921.1393931

Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology. / Suzuki, Hiroaki; Kurimoto, Masanori; Yamanaka, Tadao; Takata, Hidehiro; Makino, Hiroshi; Shinohara, Hirofumi.

Proceedings of the International Symposium on Low Power Electronics and Design. 2008. p. 15-20.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suzuki, H, Kurimoto, M, Yamanaka, T, Takata, H, Makino, H & Shinohara, H 2008, Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology. in Proceedings of the International Symposium on Low Power Electronics and Design. pp. 15-20, ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design, Bangalore, India, 08/8/11. https://doi.org/10.1145/1393921.1393931
Suzuki H, Kurimoto M, Yamanaka T, Takata H, Makino H, Shinohara H. Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology. In Proceedings of the International Symposium on Low Power Electronics and Design. 2008. p. 15-20 https://doi.org/10.1145/1393921.1393931
Suzuki, Hiroaki ; Kurimoto, Masanori ; Yamanaka, Tadao ; Takata, Hidehiro ; Makino, Hiroshi ; Shinohara, Hirofumi. / Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology. Proceedings of the International Symposium on Low Power Electronics and Design. 2008. pp. 15-20
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