Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power would correlate to the number of GPCs and the levels of GPCs, our approach targets to minimize the maximum levels and the total number of GPCs, and an ILP-based algorithm and heuristic approaches are proposed. Several experiments targeting Altera Stratix III architecture show that the proposed approach reduced the delay by up to 20% under a slight increase in total power dissipation.

Original languageEnglish
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages217-222
Number of pages6
DOIs
Publication statusPublished - 2011
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka
Duration: 2011 Aug 12011 Aug 3

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
CityFukuoka
Period11/8/111/8/3

Fingerprint

Adders
Compressors
Field programmable gate arrays (FPGA)
Inductive logic programming (ILP)
Application specific integrated circuits
Energy dissipation
Experiments

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Matsunaga, T., Kimura, S., & Matsunaga, Y. (2011). Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 217-222). [5993639] https://doi.org/10.1109/ISLPED.2011.5993639

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. / Matsunaga, Taeko; Kimura, Shinji; Matsunaga, Yusuke.

Proceedings of the International Symposium on Low Power Electronics and Design. 2011. p. 217-222 5993639.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsunaga, T, Kimura, S & Matsunaga, Y 2011, Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. in Proceedings of the International Symposium on Low Power Electronics and Design., 5993639, pp. 217-222, 17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011, Fukuoka, 11/8/1. https://doi.org/10.1109/ISLPED.2011.5993639
Matsunaga T, Kimura S, Matsunaga Y. Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. In Proceedings of the International Symposium on Low Power Electronics and Design. 2011. p. 217-222. 5993639 https://doi.org/10.1109/ISLPED.2011.5993639
Matsunaga, Taeko ; Kimura, Shinji ; Matsunaga, Yusuke. / Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. Proceedings of the International Symposium on Low Power Electronics and Design. 2011. pp. 217-222
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