Power and noise aware test using preliminary estimation

Kenji Noda; Hideaki Ito; Kazumi Hatayama; Takashi Aikyo

doi:10.1109/VDAT.2009.5158160

Power and noise aware test using preliminary estimation

Kenji Noda^*, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

Issues on power consumption and IR-drop in testing become serious problems. Some troubles, such as tester fails due to too much power consumption or IR-drop, test escapes due to slowed clock cycle, and so on, can happen in test floors. In this paper, we propose a power and noise aware scan test method. In the method, power-aware DFT and power-aware ATPG are executed based on the preliminary power/noise estimation for test. Experimental results illustrate the effect of reducing IR-drop for both shift and capture mode in scan test.

Original language	English
Title of host publication	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages	323-326
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2009.5158160
Publication status	Published - 2009
Externally published	Yes
Event	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan, Province of China Duration: 2009 Apr 28 → 2009 Apr 30

Publication series

Name	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	09/4/28 → 09/4/30

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/VDAT.2009.5158160

Cite this

Power and noise aware test using preliminary estimation. / Noda, Kenji; Ito, Hideaki; Hatayama, Kazumi et al.

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 323-326 5158160 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Noda, K, Ito, H, Hatayama, K & Aikyo, T 2009, Power and noise aware test using preliminary estimation. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158160, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, pp. 323-326, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, Province of China, 09/4/28. https://doi.org/10.1109/VDAT.2009.5158160

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title = "Power and noise aware test using preliminary estimation",

abstract = "Issues on power consumption and IR-drop in testing become serious problems. Some troubles, such as tester fails due to too much power consumption or IR-drop, test escapes due to slowed clock cycle, and so on, can happen in test floors. In this paper, we propose a power and noise aware scan test method. In the method, power-aware DFT and power-aware ATPG are executed based on the preliminary power/noise estimation for test. Experimental results illustrate the effect of reducing IR-drop for both shift and capture mode in scan test.",

author = "Kenji Noda and Hideaki Ito and Kazumi Hatayama and Takashi Aikyo",

year = "2009",

doi = "10.1109/VDAT.2009.5158160",

language = "English",

isbn = "9781424427826",

series = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

pages = "323--326",

booktitle = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

note = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 ; Conference date: 28-04-2009 Through 30-04-2009",

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AU - Noda, Kenji

AU - Ito, Hideaki

AU - Hatayama, Kazumi

AU - Aikyo, Takashi

PY - 2009

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N2 - Issues on power consumption and IR-drop in testing become serious problems. Some troubles, such as tester fails due to too much power consumption or IR-drop, test escapes due to slowed clock cycle, and so on, can happen in test floors. In this paper, we propose a power and noise aware scan test method. In the method, power-aware DFT and power-aware ATPG are executed based on the preliminary power/noise estimation for test. Experimental results illustrate the effect of reducing IR-drop for both shift and capture mode in scan test.

AB - Issues on power consumption and IR-drop in testing become serious problems. Some troubles, such as tester fails due to too much power consumption or IR-drop, test escapes due to slowed clock cycle, and so on, can happen in test floors. In this paper, we propose a power and noise aware scan test method. In the method, power-aware DFT and power-aware ATPG are executed based on the preliminary power/noise estimation for test. Experimental results illustrate the effect of reducing IR-drop for both shift and capture mode in scan test.

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BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

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Y2 - 28 April 2009 through 30 April 2009

ER -

Power and noise aware test using preliminary estimation

Abstract

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Conference

ASJC Scopus subject areas

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