Power-aware compiler controllable chip multiprocessor

Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
    Original languageEnglish
    Title of host publicationParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
    Pages427
    Number of pages1
    DOIs
    Publication statusPublished - 2007
    Event16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007 - Brasov
    Duration: 2007 Sep 152007 Sep 19

    Other

    Other16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
    CityBrasov
    Period07/9/1507/9/19

    ASJC Scopus subject areas

    • Computer Science(all)

    Cite this

    Shikano, H., Shirako, J., Wada, Y., Kimura, K., & Kasahara, H. (2007). Power-aware compiler controllable chip multiprocessor. In Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT (pp. 427). [4336255] https://doi.org/10.1109/PACT.2007.4336255

    Power-aware compiler controllable chip multiprocessor. / Shikano, Hiroaki; Shirako, Jun; Wada, Yasutaka; Kimura, Keiji; Kasahara, Hironori.

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. 2007. p. 427 4336255.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Shikano, H, Shirako, J, Wada, Y, Kimura, K & Kasahara, H 2007, Power-aware compiler controllable chip multiprocessor. in Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT., 4336255, pp. 427, 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007, Brasov, 07/9/15. https://doi.org/10.1109/PACT.2007.4336255
    Shikano H, Shirako J, Wada Y, Kimura K, Kasahara H. Power-aware compiler controllable chip multiprocessor. In Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. 2007. p. 427. 4336255 https://doi.org/10.1109/PACT.2007.4336255
    Shikano, Hiroaki ; Shirako, Jun ; Wada, Yasutaka ; Kimura, Keiji ; Kasahara, Hironori. / Power-aware compiler controllable chip multiprocessor. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. 2007. pp. 427
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