Power-aware compiler controllable chip multiprocessor

Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
Original languageEnglish
Title of host publication16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
Number of pages1
DOIs
Publication statusPublished - 2007 Dec 1
Event16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007 - Brasov, Romania
Duration: 2007 Sep 152007 Sep 19

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Conference

Conference16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
CountryRomania
CityBrasov
Period07/9/1507/9/19

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

Cite this

Shikano, H., Shirako, J., Wada, Y., Kimura, K., & Kasahara, H. (2007). Power-aware compiler controllable chip multiprocessor. In 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007 [4336255] (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT). https://doi.org/10.1109/PACT.2007.4336255