Power-efficient and slew-aware three dimensional gated clock tree synthesis

Minghao Lin; Heming Sun; Shinji Kimura

doi:10.1109/VLSI-SoC.2016.7753535

Power-efficient and slew-aware three dimensional gated clock tree synthesis

Minghao Lin, Heming Sun, Shinji Kimura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper presents a three dimensional (3D) gated clock tree synthesis (CTS) approach, which consists of two steps: 1) abstract tree topology generation; and 2) 3D gated and buffered clock routing. 3D Pair Matching (3D-PM) algorithm is proposed to generate the initial tree topology and then the proposed TSV-minimization algorithm is applied to generate TSV-aware tree topology. Based on TSV-aware tree topology, 3D gated and buffered clock tree routing is done using the proposed 3D Gated and Buffered Deferred-Merge Embedding (3D-GB-DME) algorithm. The slew constraint satisfaction is considered and the clock skew is minimized in our approach. Experimental results show that the proposed method achieves 29.11% power reduction compared with the state-of-the-art 2D work.

Original language	English
Title of host publication	2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509035618
DOIs	https://doi.org/10.1109/VLSI-SoC.2016.7753535
Publication status	Published - 2016 Nov 22
Event	24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 - Tallinn, Estonia Duration: 2016 Sept 26 → 2016 Sept 28

Other

Other	24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
Country/Territory	Estonia
City	Tallinn
Period	16/9/26 → 16/9/28

Keywords

clock gating
clock tree synthesis (CTS)
low power
three dimensional integrated circuits (3D ICs)

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SoC.2016.7753535

Cite this

Lin, M, Sun, H & Kimura, S 2016, Power-efficient and slew-aware three dimensional gated clock tree synthesis. in 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016., 7753535, Institute of Electrical and Electronics Engineers Inc., 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, 16/9/26. https://doi.org/10.1109/VLSI-SoC.2016.7753535

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title = "Power-efficient and slew-aware three dimensional gated clock tree synthesis",

abstract = "This paper presents a three dimensional (3D) gated clock tree synthesis (CTS) approach, which consists of two steps: 1) abstract tree topology generation; and 2) 3D gated and buffered clock routing. 3D Pair Matching (3D-PM) algorithm is proposed to generate the initial tree topology and then the proposed TSV-minimization algorithm is applied to generate TSV-aware tree topology. Based on TSV-aware tree topology, 3D gated and buffered clock tree routing is done using the proposed 3D Gated and Buffered Deferred-Merge Embedding (3D-GB-DME) algorithm. The slew constraint satisfaction is considered and the clock skew is minimized in our approach. Experimental results show that the proposed method achieves 29.11% power reduction compared with the state-of-the-art 2D work.",

keywords = "clock gating, clock tree synthesis (CTS), low power, three dimensional integrated circuits (3D ICs)",

author = "Minghao Lin and Heming Sun and Shinji Kimura",

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doi = "10.1109/VLSI-SoC.2016.7753535",

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T1 - Power-efficient and slew-aware three dimensional gated clock tree synthesis

AU - Lin, Minghao

AU - Sun, Heming

AU - Kimura, Shinji

PY - 2016/11/22

Y1 - 2016/11/22

N2 - This paper presents a three dimensional (3D) gated clock tree synthesis (CTS) approach, which consists of two steps: 1) abstract tree topology generation; and 2) 3D gated and buffered clock routing. 3D Pair Matching (3D-PM) algorithm is proposed to generate the initial tree topology and then the proposed TSV-minimization algorithm is applied to generate TSV-aware tree topology. Based on TSV-aware tree topology, 3D gated and buffered clock tree routing is done using the proposed 3D Gated and Buffered Deferred-Merge Embedding (3D-GB-DME) algorithm. The slew constraint satisfaction is considered and the clock skew is minimized in our approach. Experimental results show that the proposed method achieves 29.11% power reduction compared with the state-of-the-art 2D work.

AB - This paper presents a three dimensional (3D) gated clock tree synthesis (CTS) approach, which consists of two steps: 1) abstract tree topology generation; and 2) 3D gated and buffered clock routing. 3D Pair Matching (3D-PM) algorithm is proposed to generate the initial tree topology and then the proposed TSV-minimization algorithm is applied to generate TSV-aware tree topology. Based on TSV-aware tree topology, 3D gated and buffered clock tree routing is done using the proposed 3D Gated and Buffered Deferred-Merge Embedding (3D-GB-DME) algorithm. The slew constraint satisfaction is considered and the clock skew is minimized in our approach. Experimental results show that the proposed method achieves 29.11% power reduction compared with the state-of-the-art 2D work.

KW - clock gating

KW - clock tree synthesis (CTS)

KW - low power

KW - three dimensional integrated circuits (3D ICs)

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M3 - Conference contribution

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BT - 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

Y2 - 26 September 2016 through 28 September 2016

ER -

Power-efficient and slew-aware three dimensional gated clock tree synthesis

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Keywords

ASJC Scopus subject areas

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