Power-efficient and slew-aware three dimensional gated clock tree synthesis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents a three dimensional (3D) gated clock tree synthesis (CTS) approach, which consists of two steps: 1) abstract tree topology generation; and 2) 3D gated and buffered clock routing. 3D Pair Matching (3D-PM) algorithm is proposed to generate the initial tree topology and then the proposed TSV-minimization algorithm is applied to generate TSV-aware tree topology. Based on TSV-aware tree topology, 3D gated and buffered clock tree routing is done using the proposed 3D Gated and Buffered Deferred-Merge Embedding (3D-GB-DME) algorithm. The slew constraint satisfaction is considered and the clock skew is minimized in our approach. Experimental results show that the proposed method achieves 29.11% power reduction compared with the state-of-the-art 2D work.

Original languageEnglish
Title of host publication2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509035618
DOIs
Publication statusPublished - 2016 Nov 22
Event24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 - Tallinn, Estonia
Duration: 2016 Sep 262016 Sep 28

Other

Other24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
CountryEstonia
CityTallinn
Period16/9/2616/9/28

Keywords

  • clock gating
  • clock tree synthesis (CTS)
  • low power
  • three dimensional integrated circuits (3D ICs)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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