Power-efficient LDPC code decoder architecture

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

Original languageEnglish
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages359-362
Number of pages4
DOIs
Publication statusPublished - 2007
EventISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR
Duration: 2007 Aug 272007 Aug 29

Other

OtherISLPED'07: 2007 International Symposium on Low Power Electronics and Design
CityPortland, OR
Period07/8/2707/8/29

    Fingerprint

Keywords

  • Clock gating
  • FIFO buffer
  • Intermediate message compression technique
  • LDPC decoder
  • Message-passing schedule

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Shimizu, K., Togawa, N., Ikenaga, T., & Goto, S. (2007). Power-efficient LDPC code decoder architecture. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 359-362) https://doi.org/10.1145/1283780.1283858