Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Kazunori Shimizu; Tatsuyuki Ishikawa; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto

doi:10.1093/ietfec/e89-a.12.3602

Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 μm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43 and a power dissipation by 29 compared to the conventional architecture based on the accelerated message-passing schedule.

Original language	English
Pages (from-to)	3602-3612
Number of pages	11
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E89-A
Issue number	12
DOIs	https://doi.org/10.1093/ietfec/e89-a.12.3602
Publication status	Published - 2006 Dec

Keywords

FIFO-based buffering
Low-density parity-check codes
Message-passing algorithm
Parallel LDPC decoder architecture

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

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10.1093/ietfec/e89-a.12.3602

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Power-efficient LDPC decoder architecture based on accelerated message-passing schedule. / Shimizu, Kazunori; Ishikawa, Tatsuyuki; Togawa, Nozomu ; Ikenaga, Takeshi; Goto, Satoshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 12, 12.2006, p. 3602-3612.

Research output: Contribution to journal › Article › peer-review

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AB - In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 μm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43 and a power dissipation by 29 compared to the conventional architecture based on the accelerated message-passing schedule.

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Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

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Keywords

ASJC Scopus subject areas

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