Abstract
In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 μm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43 and a power dissipation by 29 compared to the conventional architecture based on the accelerated message-passing schedule.
Original language | English |
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Pages (from-to) | 3602-3612 |
Number of pages | 11 |
Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
Volume | E89-A |
Issue number | 12 |
DOIs | |
Publication status | Published - 2006 Dec |
Keywords
- FIFO-based buffering
- Low-density parity-check codes
- Message-passing algorithm
- Parallel LDPC decoder architecture
ASJC Scopus subject areas
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics