Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Research output: Contribution to journalArticle

5 Citations (Scopus)


In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 μm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43 and a power dissipation by 29 compared to the conventional architecture based on the accelerated message-passing schedule.

Original languageEnglish
Pages (from-to)3602-3612
Number of pages11
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number12
Publication statusPublished - 2006 Dec



  • FIFO-based buffering
  • Low-density parity-check codes
  • Message-passing algorithm
  • Parallel LDPC decoder architecture

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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