Power-efficient partitioning and cluster generation design for application-specific network-on-chip

Jiayi Ma, Cong Hao, Wencan Zhang, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Network-on-Chip (NoC) is a promising solution for System-on-Chip (SoC) challenges. In this work, we present a Decompose and Cluster generation Refinement (DCR) algorithm to find minimum power consumption simultaneously. A two-stage method is proposed for decompose and cluster generation step to generate solutions with lower power. Refinement step explores optimal positions and adjusts clusters for selected solutions to find balanced point between power consumption and CPU time. Experimental results show that the proposed method outperforms the existing work.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages83-84
Number of pages2
ISBN (Electronic)9781467393089
DOIs
Publication statusPublished - 2016 Dec 27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 232016 Oct 26

Other

Other13th International SoC Design Conference, ISOCC 2016
CountryKorea, Republic of
CityJeju
Period16/10/2316/10/26

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Keywords

  • Clustering
  • Network-on-chip
  • Partitioning

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation

Cite this

Ma, J., Hao, C., Zhang, W., & Yoshimura, T. (2016). Power-efficient partitioning and cluster generation design for application-specific network-on-chip. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 83-84). [7799744] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799744