Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90nm CMOS and an additional 100nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles.

Original languageEnglish
Article number04DE08
JournalJapanese Journal of Applied Physics
Volume54
Issue number4
DOIs
Publication statusPublished - 2015 Apr 1
Externally publishedYes

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sleep
microprocessors
Microprocessor chips
controllers
education
Controllers
Networks (circuits)
Processing
chips
Magnetoelectronics
Power control
clocks
Clocks
CMOS
cycles
energy
Sleep

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation. / Koike, Hiroki; Ohsawa, Takashi; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo.

In: Japanese Journal of Applied Physics, Vol. 54, No. 4, 04DE08, 01.04.2015.

Research output: Contribution to journalArticle

Koike, Hiroki ; Ohsawa, Takashi ; Miura, Sadahiko ; Honjo, Hiroaki ; Ikeda, Shoji ; Hanyu, Takahiro ; Ohno, Hideo ; Endoh, Tetsuo. / Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation. In: Japanese Journal of Applied Physics. 2015 ; Vol. 54, No. 4.
@article{aac27010e4164110905d82f0f023040d,
title = "Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation",
abstract = "A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90nm CMOS and an additional 100nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10{\%}, under the condition of a sufficient number of idle clock cycles.",
author = "Hiroki Koike and Takashi Ohsawa and Sadahiko Miura and Hiroaki Honjo and Shoji Ikeda and Takahiro Hanyu and Hideo Ohno and Tetsuo Endoh",
year = "2015",
month = "4",
day = "1",
doi = "10.7567/JJAP.54.04DE08",
language = "English",
volume = "54",
journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",
issn = "0021-4922",
publisher = "Japan Society of Applied Physics",
number = "4",

}

TY - JOUR

T1 - Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

AU - Koike, Hiroki

AU - Ohsawa, Takashi

AU - Miura, Sadahiko

AU - Honjo, Hiroaki

AU - Ikeda, Shoji

AU - Hanyu, Takahiro

AU - Ohno, Hideo

AU - Endoh, Tetsuo

PY - 2015/4/1

Y1 - 2015/4/1

N2 - A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90nm CMOS and an additional 100nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles.

AB - A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90nm CMOS and an additional 100nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles.

UR - http://www.scopus.com/inward/record.url?scp=84926387859&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84926387859&partnerID=8YFLogxK

U2 - 10.7567/JJAP.54.04DE08

DO - 10.7567/JJAP.54.04DE08

M3 - Article

AN - SCOPUS:84926387859

VL - 54

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 4

M1 - 04DE08

ER -