Power optimization of sequential circuits using switching activity based clock gating

Xin Man, Takashi Horiyama, Shinji Kimura

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.

Original languageEnglish
Pages (from-to)2472-2480
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE93-A
Issue number12
DOIs
Publication statusPublished - 2010 Dec

Fingerprint

Circuit Switching
Sequential circuits
Signal Control
Clocks
Optimization
Networks (circuits)
Logic
Benchmark
Signal Extraction
Cost reduction
Power Consumption
Insertion
Optimization Methods
Layout
Correctness
Switch
Electric power utilization
Switches
Costs
Simulation

Keywords

  • Automatic clock gating generation
  • BDD
  • Dynamic power reduction
  • Low power

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

Power optimization of sequential circuits using switching activity based clock gating. / Man, Xin; Horiyama, Takashi; Kimura, Shinji.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E93-A, No. 12, 12.2010, p. 2472-2480.

Research output: Contribution to journalArticle

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