Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Multicore processors have become mainstream computer architecture to go beyond the performance and powerefficiency limits of single-core processors. To achieve low power consumption and high performance on multicores, parallelizing compilers take on an important role. This paper describes the performance of a compiler-based power reduction scheme cooperating with OSCAR multigrain parallelizing compiler on a newly developed 8-way SH4A low power multicore chip for consumer electronics, which supports DVFS (Dynamic Voltage and Frequency Scaling) and Clock/Power Gating. Using hardware parameters and parallelized program information, OSCAR compiler determines suitable voltage and frequency of each active processor core and appropriate schedule of clock gating and power gating. Performance experiments shows the compiler reduces consumed power by 88.3%, namely from 5.68 W to 0.67 W, for real-time secure AAC Encoding and 73.5%, namely from 5.73 W to 1.52 W, for real-time MPEG2 Decoding on 8 core execution.

    Original languageEnglish
    Title of host publication2008 International SoC Design Conference, ISOCC 2008
    Volume1
    DOIs
    Publication statusPublished - 2008
    Event2008 International SoC Design Conference, ISOCC 2008 - Busan
    Duration: 2008 Nov 242008 Nov 25

    Other

    Other2008 International SoC Design Conference, ISOCC 2008
    CityBusan
    Period08/11/2408/11/25

    Fingerprint

    Clocks
    Computer architecture
    Consumer electronics
    Decoding
    Microprocessor chips
    Electric power utilization
    Hardware
    Electric potential
    Experiments
    Dynamic frequency scaling
    Voltage scaling

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Software

    Cite this

    Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler. / Shirako, Jun; Kimura, Keiji; Kasahara, Hironori.

    2008 International SoC Design Conference, ISOCC 2008. Vol. 1 2008. 4815571.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Shirako, J, Kimura, K & Kasahara, H 2008, Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler. in 2008 International SoC Design Conference, ISOCC 2008. vol. 1, 4815571, 2008 International SoC Design Conference, ISOCC 2008, Busan, 08/11/24. https://doi.org/10.1109/SOCDC.2008.4815571
    Shirako, Jun ; Kimura, Keiji ; Kasahara, Hironori. / Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler. 2008 International SoC Design Conference, ISOCC 2008. Vol. 1 2008.
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    abstract = "Multicore processors have become mainstream computer architecture to go beyond the performance and powerefficiency limits of single-core processors. To achieve low power consumption and high performance on multicores, parallelizing compilers take on an important role. This paper describes the performance of a compiler-based power reduction scheme cooperating with OSCAR multigrain parallelizing compiler on a newly developed 8-way SH4A low power multicore chip for consumer electronics, which supports DVFS (Dynamic Voltage and Frequency Scaling) and Clock/Power Gating. Using hardware parameters and parallelized program information, OSCAR compiler determines suitable voltage and frequency of each active processor core and appropriate schedule of clock gating and power gating. Performance experiments shows the compiler reduces consumed power by 88.3{\%}, namely from 5.68 W to 0.67 W, for real-time secure AAC Encoding and 73.5{\%}, namely from 5.73 W to 1.52 W, for real-time MPEG2 Decoding on 8 core execution.",
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