Power reduction through specific instruction scheduling based on hardware/software Co-design

Zhao Kang, Bian Jinian, Jiang Chenqian, Dong Sheqin, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, an instruction-level power reduction model for the low power System-on-a-Chip is proposed, which combines the hardware and software design together. Firstly, to reduce the power consumption via hardware design, this model is equipped with a specific instruction extraction process, which utilizes a sub-graph matching algorithm. Then a scheduling algorithm is integrated in this model to achieve power compression via reducing the memory access number. Finally, a set of Fir filter programs are power-driven optimized using the proposed model based on hardware/software co-design strategy, and the experimental results indicate that this model can reduce the power consumption effectively.

Original languageEnglish
Title of host publicationASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Pages193-196
Number of pages4
DOIs
Publication statusPublished - 2007
Event2007 7th International Conference on ASIC, ASICON 2007 - Guilin
Duration: 2007 Oct 262007 Oct 29

Other

Other2007 7th International Conference on ASIC, ASICON 2007
CityGuilin
Period07/10/2607/10/29

Fingerprint

Scheduling
Hardware
Electric power utilization
Software design
Scheduling algorithms
Data storage equipment

Keywords

  • Hardware/software co-design
  • Power reduction
  • Scheduling
  • SoC
  • Specific instruction

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kang, Z., Jinian, B., Chenqian, J., Sheqin, D., & Goto, S. (2007). Power reduction through specific instruction scheduling based on hardware/software Co-design. In ASICON 2007 - 2007 7th International Conference on ASIC Proceeding (pp. 193-196). [4415600] https://doi.org/10.1109/ICASIC.2007.4415600

Power reduction through specific instruction scheduling based on hardware/software Co-design. / Kang, Zhao; Jinian, Bian; Chenqian, Jiang; Sheqin, Dong; Goto, Satoshi.

ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. p. 193-196 4415600.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kang, Z, Jinian, B, Chenqian, J, Sheqin, D & Goto, S 2007, Power reduction through specific instruction scheduling based on hardware/software Co-design. in ASICON 2007 - 2007 7th International Conference on ASIC Proceeding., 4415600, pp. 193-196, 2007 7th International Conference on ASIC, ASICON 2007, Guilin, 07/10/26. https://doi.org/10.1109/ICASIC.2007.4415600
Kang Z, Jinian B, Chenqian J, Sheqin D, Goto S. Power reduction through specific instruction scheduling based on hardware/software Co-design. In ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. p. 193-196. 4415600 https://doi.org/10.1109/ICASIC.2007.4415600
Kang, Zhao ; Jinian, Bian ; Chenqian, Jiang ; Sheqin, Dong ; Goto, Satoshi. / Power reduction through specific instruction scheduling based on hardware/software Co-design. ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. pp. 193-196
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