Practically scalable floorplanning with voltage island generation

Song Chen, Xiaolin Zhang, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, we propose a method of floorplanning with voltage island generation for system-on-chips (SoC) designs, which is deeply coupled with voltage island partitioning and voltage assignment, and has a good scalability. Floorplans with voltage islands are represented using nested Sequence Pairs, where the cores involved in the same voltage island consecutively appear in the sequences. Starting from a randomly generated initial floorplan, where each non chip-level core occupies an individual voltage island, we iteratively improve the solution by removing a core from the floorplan, then, inserting back the core by trying all the possible O(n 2) block positions, which are defined as the combinations of insertion points and voltage islands. An almost linear algorithm is devised to roughly but quickly filter many worse block positions, in each iteration, considering fixed-outline constraints, wirelength, power, power/ground routing resources, and level shifters. Compared with the latest work, the proposed method shows 9.74% and 21.04% improvements respectively on the wirelength and power when all the blocks are hard. When soft blocks are involved, the proposed method shows 12.38% wirelength reduction and 3.10% more power saving with a penalty of 7.5% whitespace. Moreover, more than 20X speedups can be obtained for the large test cases.

Original languageEnglish
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages27-32
Number of pages6
DOIs
Publication statusPublished - 2012
Event2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA
Duration: 2012 Jul 302012 Aug 1

Other

Other2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
CityRedondo Beach, CA
Period12/7/3012/8/1

Fingerprint

Electric potential
Core levels
Scalability

Keywords

  • floorplanning
  • low power
  • sequence pair
  • voltage islands

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chen, S., Zhang, X., & Yoshimura, T. (2012). Practically scalable floorplanning with voltage island generation. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 27-32) https://doi.org/10.1145/2333660.2333669

Practically scalable floorplanning with voltage island generation. / Chen, Song; Zhang, Xiaolin; Yoshimura, Takeshi.

Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 27-32.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chen, S, Zhang, X & Yoshimura, T 2012, Practically scalable floorplanning with voltage island generation. in Proceedings of the International Symposium on Low Power Electronics and Design. pp. 27-32, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, 12/7/30. https://doi.org/10.1145/2333660.2333669
Chen S, Zhang X, Yoshimura T. Practically scalable floorplanning with voltage island generation. In Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 27-32 https://doi.org/10.1145/2333660.2333669
Chen, Song ; Zhang, Xiaolin ; Yoshimura, Takeshi. / Practically scalable floorplanning with voltage island generation. Proceedings of the International Symposium on Low Power Electronics and Design. 2012. pp. 27-32
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