Precise timing verification of logic circuits under combined delay model

Shinji Kimura; Shigemi Kashima; Hiromasa Haneda

doi:10.1109/iccad.1992.279317

Precise timing verification of logic circuits under combined delay model

Shinji Kimura^*, Shigemi Kashima, Hiromasa Haneda

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so.

Original language	English
Title of host publication	IEEE/ACM International Conference on Computer-Aided Design
Publisher	Publ by IEEE
Pages	526-529
Number of pages	4
ISBN (Print)	0818630108, 9780818630101
DOIs	https://doi.org/10.1109/iccad.1992.279317
Publication status	Published - 1992 Jan 1
Externally published	Yes
Event	IEEE/ACM International Conference on Computer-Aided Design - ICCAD '92 - Santa Clara, CA, USA Duration: 1992 Nov 8 → 1992 Nov 12

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design

Other

Other	IEEE/ACM International Conference on Computer-Aided Design - ICCAD '92
City	Santa Clara, CA, USA
Period	92/11/8 → 92/11/12

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/iccad.1992.279317

Cite this

Kimura, S, Kashima, S & Haneda, H 1992, Precise timing verification of logic circuits under combined delay model. in IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design, Publ by IEEE, pp. 526-529, IEEE/ACM International Conference on Computer-Aided Design - ICCAD '92, Santa Clara, CA, USA, 92/11/8. https://doi.org/10.1109/iccad.1992.279317

@inproceedings{303d179e795a4e99bdd10708a33de258,

title = "Precise timing verification of logic circuits under combined delay model",

abstract = "The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so.",

author = "Shinji Kimura and Shigemi Kashima and Hiromasa Haneda",

year = "1992",

month = jan,

day = "1",

doi = "10.1109/iccad.1992.279317",

language = "English",

isbn = "0818630108",

series = "IEEE/ACM International Conference on Computer-Aided Design",

publisher = "Publ by IEEE",

pages = "526--529",

booktitle = "IEEE/ACM International Conference on Computer-Aided Design",

note = "IEEE/ACM International Conference on Computer-Aided Design - ICCAD '92 ; Conference date: 08-11-1992 Through 12-11-1992",

}

TY - GEN

T1 - Precise timing verification of logic circuits under combined delay model

AU - Kimura, Shinji

AU - Kashima, Shigemi

AU - Haneda, Hiromasa

PY - 1992/1/1

Y1 - 1992/1/1

N2 - The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so.

AB - The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so.

UR - http://www.scopus.com/inward/record.url?scp=0026965950&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026965950&partnerID=8YFLogxK

U2 - 10.1109/iccad.1992.279317

DO - 10.1109/iccad.1992.279317

M3 - Conference contribution

AN - SCOPUS:0026965950

SN - 0818630108

SN - 9780818630101

T3 - IEEE/ACM International Conference on Computer-Aided Design

SP - 526

EP - 529

BT - IEEE/ACM International Conference on Computer-Aided Design

PB - Publ by IEEE

T2 - IEEE/ACM International Conference on Computer-Aided Design - ICCAD '92

Y2 - 8 November 1992 through 12 November 1992

ER -

Precise timing verification of logic circuits under combined delay model

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this