Precise timing verification of logic circuits under combined delay model

Shinji Kimura, Shigemi Kashima, Hiromasa Haneda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so.

Original languageEnglish
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design
Place of PublicationLos Alamitos, CA, United States
PublisherPubl by IEEE
Pages526-529
Number of pages4
ISBN (Print)0818630108
Publication statusPublished - 1992
Externally publishedYes
EventIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92 - Santa Clara, CA, USA
Duration: 1992 Nov 81992 Nov 12

Other

OtherIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92
CitySanta Clara, CA, USA
Period92/11/892/11/12

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kimura, S., Kashima, S., & Haneda, H. (1992). Precise timing verification of logic circuits under combined delay model. In IEEE/ACM International Conference on Computer-Aided Design (pp. 526-529). Publ by IEEE.