Preciseness of discrete time verification

Shinji Kimura, Shunsuke Tsubota, Hiromasa Haneda

Research output: Contribution to journalArticle

Abstract

The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the discrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then us is the expected unit time.

Original languageEnglish
Pages (from-to)1755-1756
Number of pages2
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE76-A
Issue number10
Publication statusPublished - 1993 Oct
Externally publishedYes

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Logic circuits
Time delay
Discrete-time
Unit
Delay Time
Continuous Time
Logic
Interval
Theorem

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Electrical and Electronic Engineering

Cite this

Preciseness of discrete time verification. / Kimura, Shinji; Tsubota, Shunsuke; Haneda, Hiromasa.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E76-A, No. 10, 10.1993, p. 1755-1756.

Research output: Contribution to journalArticle

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