Abstract
Interconnect reduction is one of the key issues in high-level synthesis. In this paper, we propose a primal-dual based method to solve the functional unit (FU) and register binding simultaneously while minimizing the global interconnection. Specifically, the binding problem is formulated as a min-cost network flow based on splitting weighted and order compatibility graphs (SWOCGs). The interconnect sharing among registers and FUs are maximized by binding the the operations or variables on the same path to the same FUs or registers according to the flow. Experimental results show that, compared with the previous greedy method [7], our proposed algorithm achieves an average 4.8% further reduction in global interconnection for a suite of benchmarks.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781479984831 |
| DOIs | |
| Publication status | Published - 2016 Jul 19 |
| Event | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China Duration: 2015 Nov 3 → 2015 Nov 6 |
Other
| Other | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 |
|---|---|
| Country | China |
| City | Chengdu |
| Period | 15/11/3 → 15/11/6 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Primal-dual method based simultaneous functional unit and register binding. / Ni, Jianmo; Hao, Cong; Wang, Nan; Ai, Qian; Yoshimura, Takeshi.
Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7516909.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Primal-dual method based simultaneous functional unit and register binding
AU - Ni, Jianmo
AU - Hao, Cong
AU - Wang, Nan
AU - Ai, Qian
AU - Yoshimura, Takeshi
PY - 2016/7/19
Y1 - 2016/7/19
N2 - Interconnect reduction is one of the key issues in high-level synthesis. In this paper, we propose a primal-dual based method to solve the functional unit (FU) and register binding simultaneously while minimizing the global interconnection. Specifically, the binding problem is formulated as a min-cost network flow based on splitting weighted and order compatibility graphs (SWOCGs). The interconnect sharing among registers and FUs are maximized by binding the the operations or variables on the same path to the same FUs or registers according to the flow. Experimental results show that, compared with the previous greedy method [7], our proposed algorithm achieves an average 4.8% further reduction in global interconnection for a suite of benchmarks.
AB - Interconnect reduction is one of the key issues in high-level synthesis. In this paper, we propose a primal-dual based method to solve the functional unit (FU) and register binding simultaneously while minimizing the global interconnection. Specifically, the binding problem is formulated as a min-cost network flow based on splitting weighted and order compatibility graphs (SWOCGs). The interconnect sharing among registers and FUs are maximized by binding the the operations or variables on the same path to the same FUs or registers according to the flow. Experimental results show that, compared with the previous greedy method [7], our proposed algorithm achieves an average 4.8% further reduction in global interconnection for a suite of benchmarks.
UR - http://www.scopus.com/inward/record.url?scp=84982274177&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84982274177&partnerID=8YFLogxK
U2 - 10.1109/ASICON.2015.7516909
DO - 10.1109/ASICON.2015.7516909
M3 - Conference contribution
AN - SCOPUS:84982274177
BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
PB - Institute of Electrical and Electronics Engineers Inc.
ER -