Abstract
A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.
Original language | English |
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Journal | IEEE Transactions on Electron Devices |
Volume | ED-34 |
Issue number | 12 |
Publication status | Published - 1987 Dec 1 |
Externally published | Yes |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering