PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.

Noriyoshi Yamauchi

PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.

Noriyoshi Yamauchi^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

Original language	English
Journal	IEEE Transactions on Electron Devices
Volume	ED-34
Issue number	12
Publication status	Published - 1987 Dec 1
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.",

abstract = "A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.",

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PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.

Abstract

ASJC Scopus subject areas

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