PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.

Noriyoshi Yamauchi

PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.

Graduate School of Information, Production and Systems

Research output: Contribution to journal › Article

Abstract

A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

Original language	English
Journal	IEEE Transactions on Electron Devices
Volume	ED-34
Issue number	12
Publication status	Published - 1987 Dec 1

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Yamauchi, N. (1987). PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA. IEEE Transactions on Electron Devices, ED-34(12).

@article{eda8952b976d4657baf603a98c7d5ac0,

title = "PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.",

abstract = "A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.",

author = "Noriyoshi Yamauchi",

year = "1987",

month = dec,

day = "1",

language = "English",

volume = "ED-34",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.

AU - Yamauchi, Noriyoshi

PY - 1987/12/1

Y1 - 1987/12/1

N2 - A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

AB - A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

UR - http://www.scopus.com/inward/record.url?scp=0023596401&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023596401&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0023596401

VL - ED-34

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 12

ER -