Abstract
A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.
| Original language | English |
|---|---|
| Journal | IEEE Transactions on Electron Devices |
| Volume | ED-34 |
| Issue number | 12 |
| Publication status | Published - 1987 Dec |
| Externally published | Yes |
Fingerprint
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Physics and Astronomy (miscellaneous)
Cite this
PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA. / Yamauchi, Noriyoshi.
In: IEEE Transactions on Electron Devices, Vol. ED-34, No. 12, 12.1987.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.
AU - Yamauchi, Noriyoshi
PY - 1987/12
Y1 - 1987/12
N2 - A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.
AB - A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.
UR - http://www.scopus.com/inward/record.url?scp=0023596401&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0023596401&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0023596401
VL - ED-34
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 12
ER -