Process variation aware D-Flip-Flop design using regression analysis

Shinichi Nishizawa, Hidetoshi Onodera

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equations for transistor widths tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.

Original languageEnglish
Title of host publication2018 19th International Symposium on Quality Electronic Design, ISQED 2018
PublisherIEEE Computer Society
Pages88-93
Number of pages6
ISBN (Electronic)9781538612149
DOIs
Publication statusPublished - 2018 May 9
Externally publishedYes
Event19th International Symposium on Quality Electronic Design, ISQED 2018 - Santa Clara, United States
Duration: 2018 Mar 132018 Mar 14

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2018-March
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other19th International Symposium on Quality Electronic Design, ISQED 2018
Country/TerritoryUnited States
CitySanta Clara
Period18/3/1318/3/14

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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