TY - GEN
T1 - Process variation aware D-Flip-Flop design using regression analysis
AU - Nishizawa, Shinichi
AU - Onodera, Hidetoshi
N1 - Funding Information:
This work has been partly supported by JSPS KAKENHI JP16H01713 and JP17K12657. This work is also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., and Menter Graphics, Inc.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/5/9
Y1 - 2018/5/9
N2 - This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equations for transistor widths tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
AB - This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equations for transistor widths tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
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U2 - 10.1109/ISQED.2018.8357270
DO - 10.1109/ISQED.2018.8357270
M3 - Conference contribution
AN - SCOPUS:85047946177
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 88
EP - 93
BT - 2018 19th International Symposium on Quality Electronic Design, ISQED 2018
PB - IEEE Computer Society
T2 - 19th International Symposium on Quality Electronic Design, ISQED 2018
Y2 - 13 March 2018 through 14 March 2018
ER -