TY - GEN
T1 - Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics
AU - Nishizawa, Shinichi
AU - Ito, Kazuhito
N1 - Funding Information:
This work has been partly supported by JSPS KAKENHI JP17K12657. This work is also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., and Mentor Graphics, Inc. Test chip is provided from Prof. Onodera of Kyoto University, Japan. LSI tester is provided from Prof. Kobayashi of Kyoto Institute of Technology, Japan.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/5
Y1 - 2020/5
N2 - Extraction method of process variation is proposed. Process monitor circuits are widely used for the extraction of process variation, however adding special purpose circuit increase the silicon area. Usually, silicon chips are tested electrically and functionally after the fabrication. IDDQ test is an electrical test which measures leakage current and find the fault in the target chip. Scan-test is a functional test which inputs and measures the internal signal vector using scan-flip-flop. We propose to an extraction method of process variation utilizing IDDQ test and retention characteristics of scan-flip-flop. This method enables process variation extraction without any extra process monitor circuit. Test structures are implemented into silicon chips and result shows global variation shift is extracted as threshold voltage shift.
AB - Extraction method of process variation is proposed. Process monitor circuits are widely used for the extraction of process variation, however adding special purpose circuit increase the silicon area. Usually, silicon chips are tested electrically and functionally after the fabrication. IDDQ test is an electrical test which measures leakage current and find the fault in the target chip. Scan-test is a functional test which inputs and measures the internal signal vector using scan-flip-flop. We propose to an extraction method of process variation utilizing IDDQ test and retention characteristics of scan-flip-flop. This method enables process variation extraction without any extra process monitor circuit. Test structures are implemented into silicon chips and result shows global variation shift is extracted as threshold voltage shift.
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U2 - 10.1109/ICMTS48187.2020.9107931
DO - 10.1109/ICMTS48187.2020.9107931
M3 - Conference contribution
AN - SCOPUS:85086448610
T3 - IEEE International Conference on Microelectronic Test Structures
BT - 2020 IEEE 33rd International Conference on Microelectronic Test Structures, ICMTS 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 33rd IEEE International Conference on Microelectronic Test Structures, ICMTS 2020
Y2 - 4 May 2020 through 18 May 2020
ER -